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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children 13625e7b9d1f
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1 #ifndef CYGONCE_KERNEL_INTR_HXX
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2 #define CYGONCE_KERNEL_INTR_HXX
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3
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4 //==========================================================================
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5 //
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6 // intr.hxx
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7 //
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8 // Interrupt class declaration(s)
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9 //
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10 //==========================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //==========================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg
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47 // Contributors: nickg
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48 // Date: 1997-09-09
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49 // Purpose: Define Interrupt class interfaces
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50 // Description: The classes defined here provide the APIs for handling
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51 // interrupts.
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52 // Usage: #include "intr.hxx"
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53 //
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54 //
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55 //####DESCRIPTIONEND####
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56 //
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57 //==========================================================================
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58
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59 #include <cyg/kernel/ktypes.h>
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60
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61 #include <cyg/kernel/smp.hxx>
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62
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63 // -------------------------------------------------------------------------
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64 // Default definitions
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65
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66 // Some HALs define the ISR table to be a different size to the number
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67 // of ISR vectors. These HALs will define CYGNUM_HAL_ISR_TABLE_SIZE. All
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68 // other HALs will have the table size equal to the number of vectors.
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69
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70 #ifndef CYGNUM_HAL_ISR_TABLE_SIZE
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71 # define CYGNUM_HAL_ISR_TABLE_SIZE CYGNUM_HAL_ISR_COUNT
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72 #endif
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73
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74 // -------------------------------------------------------------------------
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75 // Function prototype typedefs
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76
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77
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78 // VSR = Vector Service Routine. This is the code attached directly to an
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79 // interrupt vector. It is very architecture/platform specific and usually
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80 // must be written in assembler.
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81
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82 typedef void cyg_VSR();
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83
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84 // ISR = Interrupt Service Routine. This is called from the default
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85 // VSR in response to an interrupt. It may access shared data but may
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86 // not call kernel routines. The return value may be
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87 // Cyg_Interrupt::HANDLED and/or Cyg_Interrupt::CALL_DSR.
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88
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89 typedef cyg_uint32 cyg_ISR(cyg_vector vector, CYG_ADDRWORD data);
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90
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91 // DSR = Deferred Service Routine. This is called if the ISR returns
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92 // the Cyg_Interrupt::CALL_DSR bit. It is called at a "safe" point in
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93 // the kernel where it may make calls on kernel routines. The count
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94 // argument indicates how many times the ISR has asked for the DSR to
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95 // be posted since the last time the DSR ran.
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96
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97 typedef void cyg_DSR(cyg_vector vector, cyg_ucount32 count, CYG_ADDRWORD data);
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98
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99 // -------------------------------------------------------------------------
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100 // Include HAL definitions
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101
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102 class Cyg_Interrupt;
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103
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104 #include <cyg/hal/hal_arch.h>
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105
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106 #include <cyg/hal/hal_intr.h>
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107
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108 #ifndef HAL_INTERRUPT_STACK_CALL_PENDING_DSRS
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109 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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110 Cyg_Interrupt::call_pending_DSRs_inner()
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111 #endif
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112
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113 externC void interrupt_end(
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114 cyg_uint32 isr_ret,
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115 Cyg_Interrupt *intr,
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116 HAL_SavedRegisters *ctx
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117 );
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118
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119 externC void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
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120 externC void cyg_interrupt_call_pending_DSRs( void );
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121
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122 // -------------------------------------------------------------------------
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123 // Interrupt class. This both represents each interrupt and provides a static
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124 // interface for controlling the interrupt hardware.
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125
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126 class Cyg_Interrupt
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127 {
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128
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129 friend class Cyg_Scheduler;
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130 friend void interrupt_end( cyg_uint32,
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131 Cyg_Interrupt *,
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132 HAL_SavedRegisters *);
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133 friend void cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj );
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134 friend void cyg_interrupt_call_pending_DSRs( void );
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135
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136 cyg_vector vector; // Interrupt vector
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137
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138 cyg_priority priority; // Queuing priority
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139
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140 cyg_ISR *isr; // Pointer to ISR
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141
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142 cyg_DSR *dsr; // Pointer to DSR
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143
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144 CYG_ADDRWORD data; // Data pointer
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145
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146
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147
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148 // DSR handling interface called by the scheduler
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149
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150 // Check for pending DSRs
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151 static cyg_bool DSRs_pending();
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152
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153 // Call any pending DSRs
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154 static void call_pending_DSRs();
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155 static void call_pending_DSRs_inner();
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156
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157 // DSR handling interface called by the scheduler and HAL
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158 // interrupt arbiters.
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159
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160 void post_dsr(); // Post the DSR for this interrupt
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161
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162
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163
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164 // Data structures for handling DSR calls. We implement two DSR
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165 // handling mechanisms, a list based one and a table based
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166 // one. The list based mechanism is safe with respect to temporary
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167 // overloads and will not run out of resource. However it requires
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168 // extra data per interrupt object, and interrupts must be turned
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169 // off briefly when delivering the DSR. The table based mechanism
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170 // does not need unnecessary interrupt switching, but may be prone
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171 // to overflow on overload. However, since a correctly programmed
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172 // real time application should not experience such a condition,
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173 // the table based mechanism is more efficient for real use. The
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174 // list based mechainsm is enabled by default since it is safer to
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175 // use during development.
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176
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177 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
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178
182
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179 static Cyg_Interrupt *dsr_table[CYGNUM_KERNEL_CPU_MAX]
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180 [CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]
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181 CYGBLD_ANNOTATE_VARIABLE_INTR;
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182
182
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183 static cyg_ucount32 dsr_table_head[CYGNUM_KERNEL_CPU_MAX]
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184 CYGBLD_ANNOTATE_VARIABLE_INTR;
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185
182
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186 static volatile cyg_ucount32 dsr_table_tail[CYGNUM_KERNEL_CPU_MAX]
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187 CYGBLD_ANNOTATE_VARIABLE_INTR;
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188
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189 #endif
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190 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
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191
177
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192 // Number of DSR posts made
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193 volatile cyg_ucount32 dsr_count CYGBLD_ANNOTATE_VARIABLE_INTR;
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194
177
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195 // next DSR in list
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196 Cyg_Interrupt* volatile next_dsr CYGBLD_ANNOTATE_VARIABLE_INTR;
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197
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198 // static list of pending DSRs
182
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199 static Cyg_Interrupt* volatile dsr_list[CYGNUM_KERNEL_CPU_MAX]
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200 CYGBLD_ANNOTATE_VARIABLE_INTR;
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201
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202 #endif
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203
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204 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
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205
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206 // The default mechanism for handling interrupts is to attach just
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207 // one Interrupt object to each vector. In some cases, and on some
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208 // hardware, this is not possible, and each vector must carry a chain
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209 // of interrupts.
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210
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211 Cyg_Interrupt *next; // Next Interrupt in list
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212
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213 // Chaining ISR inserted in HAL vector
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214 static cyg_uint32 chain_isr(cyg_vector vector, CYG_ADDRWORD data);
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215
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216 // Table of interrupt chains
177
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217 static Cyg_Interrupt *chain_list[CYGNUM_HAL_ISR_TABLE_SIZE];
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218
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219 #endif
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220
177
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221 // Interrupt disable data. Interrupt disable can be nested. On
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222 // each CPU this is controlled by disable_counter[cpu]. When the
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223 // counter is first incremented from zero to one, the
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224 // interrupt_disable_spinlock is claimed using spin_intsave(), the
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225 // original interrupt enable state being saved in
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226 // interrupt_disable_state[cpu]. When the counter is decremented
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227 // back to zero the spinlock is cleared using clear_intsave().
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228
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229 // The spinlock is necessary in SMP systems since a thread
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230 // accessing data shared with an ISR may be scheduled on a
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231 // different CPU to the one that handles the interrupt. So, merely
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232 // blocking local interrupts would be ineffective. SMP aware
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233 // device drivers should either use their own spinlocks to protect
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234 // data, or use the API supported by this class, via
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235 // cyg_drv_isr_lock()/_unlock(). Note that it now becomes
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236 // essential that ISRs do this if they are to be SMP-compatible.
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237
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238 // In a single CPU system, this mechanism reduces to just
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239 // disabling/enabling interrupts.
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240
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241 // Disable level counter. This counts the number of times
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242 // interrupts have been disabled.
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243 static volatile cyg_int32 disable_counter[CYGNUM_KERNEL_CPU_MAX]
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244 CYGBLD_ANNOTATE_VARIABLE_INTR;
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245
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246 // Interrupt disable spinlock. This is claimed by any CPU that has
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247 // disabled interrupts via the Cyg_Interrupt API.
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248 static Cyg_SpinLock interrupt_disable_spinlock CYGBLD_ANNOTATE_VARIABLE_INTR;
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249
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250 // Saved interrupt state. When each CPU first disables interrupts
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251 // the original state of the interrupts are saved here to be
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252 // restored later.
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253 static CYG_INTERRUPT_STATE interrupt_disable_state[CYGNUM_KERNEL_CPU_MAX]
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254 CYGBLD_ANNOTATE_VARIABLE_INTR;
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255
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256
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257 public:
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258
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259 Cyg_Interrupt // Initialize interrupt
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260 (
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261 cyg_vector vector, // Vector to attach to
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262 cyg_priority priority, // Queue priority
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263 CYG_ADDRWORD data, // Data pointer
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264 cyg_ISR *isr, // Interrupt Service Routine
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265 cyg_DSR *dsr // Deferred Service Routine
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266 );
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267
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268 ~Cyg_Interrupt();
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269
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270 // ISR return values
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271 enum {
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272 HANDLED = 1, // Interrupt was handled
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273 CALL_DSR = 2 // Schedule DSR
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274 };
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275
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276 // Interrupt management
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277
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278 void attach(); // Attach to vector
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279
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280
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281 void detach(); // Detach from vector
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282
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283
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284 // Static Interrupt management functions
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285
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286 // Get the current service routine
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287 static void get_vsr(cyg_vector vector, cyg_VSR **vsr);
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288
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289 // Install a vector service routine
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290 static void set_vsr(
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291 cyg_vector vector, // hardware vector to replace
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292 cyg_VSR *vsr, // my new service routine
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293 cyg_VSR **old = NULL // pointer to old vsr, if required
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294 );
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295
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296
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297 // Static interrupt masking functions
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298
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299 // Disable interrupts at the CPU
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300 static void disable_interrupts();
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301
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302 // Re-enable CPU interrupts
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303 static void enable_interrupts();
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304
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305 // Are interrupts enabled at the CPU?
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306 static inline cyg_bool interrupts_enabled()
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307 {
177
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308 return (0 == disable_counter[CYG_KERNEL_CPU_THIS()]);
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309 }
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310
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311 // Get the vector for the following calls
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312 inline cyg_vector get_vector()
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313 {
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314 return vector;
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315 }
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316
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317 // Static PIC control functions
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318
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319 // Mask a specific interrupt in a PIC
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320 static void mask_interrupt(cyg_vector vector);
208
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321 // The same but not interrupt safe
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322 static void mask_interrupt_intunsafe(cyg_vector vector);
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323
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324 // Clear PIC mask
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325 static void unmask_interrupt(cyg_vector vector);
208
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326 // The same but not interrupt safe
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327 static void unmask_interrupt_intunsafe(cyg_vector vector);
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328
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329 // Acknowledge interrupt at PIC
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330 static void acknowledge_interrupt(cyg_vector vector);
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331
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332 // Change interrupt detection at PIC
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333 static void configure_interrupt(
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334 cyg_vector vector, // vector to control
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335 cyg_bool level, // level or edge triggered
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336 cyg_bool up // hi/lo level, rising/falling edge
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337 );
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338
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339 #ifdef CYGPKG_KERNEL_SMP_SUPPORT
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340
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341 // SMP support for associating an interrupt with a specific CPU.
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342
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343 static void set_cpu( cyg_vector, HAL_SMP_CPU_TYPE cpu );
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344 static HAL_SMP_CPU_TYPE get_cpu( cyg_vector );
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345
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346 #endif
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347 };
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348
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349 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS
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350 // -------------------------------------------------------------------------
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351 // Check for pending DSRs
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352
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353 inline cyg_bool Cyg_Interrupt::DSRs_pending()
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354 {
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355 HAL_SMP_CPU_TYPE cpu = CYG_KERNEL_CPU_THIS();
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356 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
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357
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358 return dsr_table_head[cpu] != dsr_table_tail[cpu];
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359
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360 #endif
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361 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
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362
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363 return dsr_list[cpu] != NULL;
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364
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365 #endif
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366 };
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367 #endif // CYGIMP_KERNEL_INTERRUPTS_DSRS
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368
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369 // -------------------------------------------------------------------------
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370 #endif // ifndef CYGONCE_KERNEL_INTR_HXX
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371 // EOF intr.hxx