Mercurial > nand-ecoscentric
annotate packages/hal/powerpc/arch/current/include/hal_cache.h @ 10:d3fbcdfa1b2f ecos-sw-1999-05-29
Merge from eCos master repository on 1999-05-29-00:13:11-BST
| author | jlarmour |
|---|---|
| date | Fri, 28 May 1999 16:43:09 +0000 |
| parents | 443894e2e912 |
| children | 4f2df4ab82c8 |
| rev | line source |
|---|---|
| 0 | 1 #ifndef CYGONCE_HAL_CACHE_H |
| 2 #define CYGONCE_HAL_CACHE_H | |
| 3 | |
| 4 //============================================================================= | |
| 5 // | |
| 6 // hal_cache.h | |
| 7 // | |
| 8 // HAL cache control API | |
| 9 // | |
| 10 //============================================================================= | |
| 11 //####COPYRIGHTBEGIN#### | |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Cygnus eCos Public License | |
| 15 // Version 1.0 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://sourceware.cygnus.com/ecos | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 25 // September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 29 // ------------------------------------------- |
| 30 // | |
| 31 //####COPYRIGHTEND#### | |
| 32 //============================================================================= | |
| 33 //#####DESCRIPTIONBEGIN#### | |
| 34 // | |
| 35 // Author(s): nickg | |
| 36 // Contributors: nickg | |
| 37 // Date: 1998-02-17 | |
| 38 // Purpose: Cache control API | |
| 39 // Description: The macros defined here provide the HAL APIs for handling | |
| 40 // cache control operations. | |
| 41 // Usage: | |
| 42 // #include <cyg/hal/hal_cache.h> | |
| 43 // ... | |
| 44 // | |
| 45 // | |
| 46 //####DESCRIPTIONEND#### | |
| 47 // | |
| 48 //============================================================================= | |
| 49 | |
| 50 #include <pkgconf/hal.h> | |
| 51 #include <cyg/infra/cyg_type.h> | |
| 2 | 52 |
| 0 | 53 #include <cyg/hal/ppc_regs.h> |
| 54 | |
| 55 //============================================================================= | |
| 2 | 56 // Memory mapping |
| 57 typedef struct { | |
| 58 CYG_ADDRESS virtual_addr; | |
| 59 CYG_ADDRESS physical_addr; | |
| 60 cyg_int32 size; | |
| 61 cyg_uint8 flags; | |
| 62 } cyg_memdesc_t; | |
| 63 | |
| 64 #define CYGARC_MEMDESC_CI 1 // cache inhibit | |
| 65 #define CYGARC_MEMDESC_GUARDED 2 // guarded | |
| 66 | |
| 67 //============================================================================= | |
| 0 | 68 // PowerPC simulator |
| 69 | |
| 70 #ifdef CYG_HAL_POWERPC_SIM | |
| 71 | |
| 72 //----------------------------------------------------------------------------- | |
| 73 // Cache dimensions | |
| 74 | |
| 75 // Data cache | |
| 76 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes | |
| 77 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 78 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 79 | |
| 80 // Instruction cache | |
| 81 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes | |
| 82 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 83 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 84 | |
| 85 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 86 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 87 | |
| 88 //----------------------------------------------------------------------------- | |
| 89 // Global control of data cache | |
| 90 | |
| 91 // Enable the data cache | |
| 92 #define HAL_DCACHE_ENABLE() | |
| 93 | |
| 94 // Disable the data cache | |
| 95 #define HAL_DCACHE_DISABLE() | |
| 96 | |
| 97 // Invalidate the entire cache | |
| 98 #define HAL_DCACHE_INVALIDATE_ALL() | |
| 99 | |
| 100 // Synchronize the contents of the cache with memory. | |
| 101 #define HAL_DCACHE_SYNC() | |
| 102 | |
| 2 | 103 // Query the state of the data cache |
| 104 #define HAL_DCACHE_IS_ENABLED(_state_) \ | |
| 105 CYG_MACRO_START \ | |
| 106 (_state_) = 0; \ | |
| 107 CYG_MACRO_END | |
| 108 | |
| 0 | 109 // Set the data cache refill burst size |
| 110 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 111 | |
| 112 // Set the data cache write mode | |
| 113 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 114 | |
| 115 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 116 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 117 | |
| 118 // Load the contents of the given address range into the data cache | |
| 119 // and then lock the cache so that it stays there. | |
| 120 //#define HAL_DCACHE_LOCK(_base_, _size_) | |
| 121 | |
| 122 // Undo a previous lock operation | |
| 123 //#define HAL_DCACHE_UNLOCK(_base_, _size_) | |
| 124 | |
| 2 | 125 // Unlock entire cache |
| 126 //#define HAL_DCACHE_UNLOCK_ALL() | |
| 127 | |
| 0 | 128 //----------------------------------------------------------------------------- |
| 129 // Data cache line control | |
| 130 | |
| 131 // Allocate cache lines for the given address range without reading its | |
| 132 // contents from memory. | |
| 133 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 134 | |
| 135 // Write dirty cache lines to memory and invalidate the cache entries | |
| 136 // for the given address range. | |
| 137 //#define HAL_DCACHE_FLUSH( _base_ , _size_ ) | |
| 138 | |
| 139 // Invalidate cache lines in the given range without writing to memory. | |
| 140 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) | |
| 141 | |
| 142 // Write dirty cache lines to memory for the given address range. | |
| 143 //#define HAL_DCACHE_STORE( _base_ , _size_ ) | |
| 144 | |
| 145 // Preread the given range into the cache with the intention of reading | |
| 146 // from it later. | |
| 147 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) | |
| 148 | |
| 149 // Preread the given range into the cache with the intention of writing | |
| 150 // to it later. | |
| 151 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) | |
| 152 | |
| 153 // Allocate and zero the cache lines associated with the given range. | |
| 154 //#define HAL_DCACHE_ZERO( _base_ , _size_ ) | |
| 155 | |
| 156 //----------------------------------------------------------------------------- | |
| 157 // Global control of Instruction cache | |
| 158 | |
| 159 // Enable the instruction cache | |
| 160 #define HAL_ICACHE_ENABLE() | |
| 161 | |
| 162 // Disable the instruction cache | |
| 163 #define HAL_ICACHE_DISABLE() | |
| 164 | |
| 165 // Invalidate the entire cache | |
| 166 #define HAL_ICACHE_INVALIDATE_ALL() | |
| 167 | |
| 168 // Synchronize the contents of the cache with memory. | |
| 169 #define HAL_ICACHE_SYNC() | |
| 170 | |
| 2 | 171 // Query the state of the instruction cache |
| 172 #define HAL_ICACHE_IS_ENABLED(_state_) \ | |
| 173 CYG_MACRO_START \ | |
| 174 (_state_) = 0; \ | |
| 175 CYG_MACRO_END | |
| 176 | |
| 0 | 177 // Set the instruction cache refill burst size |
| 178 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 179 | |
| 180 // Load the contents of the given address range into the instruction cache | |
| 181 // and then lock the cache so that it stays there. | |
| 182 //#define HAL_ICACHE_LOCK(_base_, _size_) | |
| 183 | |
| 184 // Undo a previous lock operation | |
| 185 //#define HAL_ICACHE_UNLOCK(_base_, _size_) | |
| 186 | |
| 2 | 187 // Unlock entire cache |
| 188 //#define HAL_ICACHE_UNLOCK_ALL() | |
| 189 | |
| 0 | 190 //----------------------------------------------------------------------------- |
| 191 // Instruction cache line control | |
| 192 | |
| 193 // Invalidate cache lines in the given range without writing to memory. | |
| 194 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 195 | |
| 196 | |
| 197 //============================================================================= | |
| 2 | 198 // Motorola MPC8xx |
| 0 | 199 |
| 2 | 200 #elif defined(CYG_HAL_POWERPC_MPC8xx) |
| 0 | 201 |
| 202 //----------------------------------------------------------------------------- | |
| 203 // Cache dimensions | |
| 204 | |
| 2 | 205 #if defined(CYG_HAL_POWERPC_MPC860) |
| 0 | 206 // Data cache |
| 207 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes | |
| 208 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 209 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 210 | |
| 211 // Instruction cache | |
| 212 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes | |
| 213 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 214 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 2 | 215 #endif // defined(CYG_HAL_POWERPC_MPC860) |
| 216 | |
| 217 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) | |
| 218 // Data cache | |
| 219 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes | |
| 220 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line | |
| 221 #define HAL_DCACHE_WAYS 2 // Associativity of the cache | |
| 222 | |
| 223 // Instruction cache | |
| 224 #define HAL_ICACHE_SIZE 2048 // Size of cache in bytes | |
| 225 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line | |
| 226 #define HAL_ICACHE_WAYS 2 // Associativity of the cache | |
| 227 #endif // defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850) | |
| 0 | 228 |
| 229 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) | |
| 230 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) | |
| 231 | |
| 232 //----------------------------------------------------------------------------- | |
| 233 // Global control of data cache | |
| 234 | |
| 235 // Enable the data cache | |
| 236 #define HAL_DCACHE_ENABLE() \ | |
| 237 asm volatile ("sync;" \ | |
| 2 | 238 "mtspr %0, %1;" \ |
| 239 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE)) | |
| 0 | 240 |
| 241 // Disable the data cache | |
| 242 #define HAL_DCACHE_DISABLE() \ | |
| 243 asm volatile ("sync;" \ | |
| 2 | 244 "mtspr %0, %1;" \ |
| 245 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD)) | |
| 0 | 246 |
| 247 // Invalidate the entire cache | |
| 2 | 248 // Note: Any locked lines will not be invalidated. |
| 249 #define HAL_DCACHE_INVALIDATE_ALL() \ | |
| 250 asm volatile ("sync;" \ | |
| 251 "mtspr %0, %1;" \ | |
| 252 : : "I" (CYGARC_REG_DC_CST), \ | |
| 253 "r" (CYGARC_REG_DC_CMD_IA)) | |
| 0 | 254 |
| 255 // Synchronize the contents of the cache with memory. | |
| 2 | 256 #define HAL_DCACHE_SYNC() \ |
| 257 CYG_MACRO_START \ | |
| 258 cyg_int32 i; \ | |
| 259 for (i = 0; i < HAL_DCACHE_SETS; i++){ \ | |
| 260 asm volatile ("sync;" \ | |
| 261 "mtspr %0, %2;" \ | |
| 262 "mtspr %1, %4;" \ | |
| 263 "mtspr %0, %3;" \ | |
| 264 "mtspr %1, %4;" \ | |
| 265 : /* no output */ \ | |
| 266 : /* %0 */ "I" (CYGARC_REG_DC_ADR), \ | |
| 267 /* %1 */ "I" (CYGARC_REG_DC_CST), \ | |
| 268 /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ | |
| 269 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ | |
| 270 /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \ | |
| 271 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \ | |
| 272 /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \ | |
| 273 } \ | |
| 0 | 274 CYG_MACRO_END |
| 2 | 275 |
| 276 // Query the state of the data cache | |
| 277 #define HAL_DCACHE_IS_ENABLED(_state_) \ | |
| 278 asm volatile ("mfspr %0, %1;" \ | |
| 279 "rlwinm %0,%0,1,31,31;" \ | |
| 280 : "=r" (_state_) : "I" (CYGARC_REG_DC_CST)) | |
| 0 | 281 |
| 282 // Set the data cache refill burst size | |
| 283 //#define HAL_DCACHE_BURST_SIZE(_size_) | |
| 284 | |
| 285 // Set the data cache write mode | |
| 286 //#define HAL_DCACHE_WRITE_MODE( _mode_ ) | |
| 287 | |
| 288 //#define HAL_DCACHE_WRITETHRU_MODE 0 | |
| 289 //#define HAL_DCACHE_WRITEBACK_MODE 1 | |
| 290 | |
| 2 | 291 |
| 292 // Load the contents of the given address range into the data cache | |
| 293 // and then lock the cache so that it stays there. | |
| 294 | |
| 295 // Restrictions: This implementation only allows a single area to be | |
| 296 // locked at any one time. This area must be 2kB or less in size. | |
| 297 | |
| 298 // Implementation: Flush entire cache, then invalidate it. This | |
| 299 // ensures that the fetched data go into way0. | |
| 0 | 300 |
| 2 | 301 #define HAL_DCACHE_LOCK(_base_, _size_) \ |
| 302 CYG_MACRO_START \ | |
| 303 cyg_int32 __scratch; \ | |
| 304 cyg_uint32 __base = (cyg_uint32)(_base_); \ | |
| 305 cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \ | |
| 306 cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \ | |
| 307 HAL_DCACHE_DISABLE(); \ | |
| 308 HAL_DCACHE_SYNC (); \ | |
| 309 HAL_DCACHE_INVALIDATE_ALL (); \ | |
| 310 HAL_DCACHE_ENABLE(); \ | |
| 311 do { \ | |
| 312 asm volatile ("lbz %0,0(%1);" \ | |
| 313 "sync;" \ | |
| 314 "mtspr %2, %4;" \ | |
| 315 "mtspr %3, %5;" \ | |
|
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d3fbcdfa1b2f
Merge from eCos master repository on 1999-05-29-00:13:11-BST
jlarmour
parents:
2
diff
changeset
|
316 : /* %0 */ "=&r" (__scratch) \ |
| 2 | 317 : /* %1 */ "b" (__base), \ |
| 318 /* %2 */ "I" (CYGARC_REG_DC_ADR), \ | |
| 319 /* %3 */ "I" (CYGARC_REG_DC_CST), \ | |
| 320 /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \ | |
| 321 |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \ | |
| 322 /* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \ | |
| 323 __l++; \ | |
| 324 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 325 } while (__count--); \ | |
| 326 CYG_MACRO_END | |
| 327 | |
| 328 | |
| 0 | 329 // Undo a previous lock operation |
| 2 | 330 |
| 331 // Implementation: Unlocks entire cache. | |
| 332 | |
| 333 #define HAL_DCACHE_UNLOCK(_base_, _size_) \ | |
| 334 HAL_DCACHE_UNLOCK_ALL() | |
| 335 | |
| 336 | |
| 337 // Unlock entire cache | |
| 338 #define HAL_DCACHE_UNLOCK_ALL() \ | |
| 339 CYG_MACRO_START \ | |
| 340 asm volatile ("sync;" \ | |
| 341 "mtspr %0, %1;" \ | |
| 342 : : "I" (CYGARC_REG_DC_CST), \ | |
| 343 "r" (CYGARC_REG_DC_CMD_UA)); \ | |
| 344 CYG_MACRO_END | |
| 345 | |
| 346 | |
| 0 | 347 |
| 348 //----------------------------------------------------------------------------- | |
| 349 // Data cache line control | |
| 350 | |
| 351 // Allocate cache lines for the given address range without reading its | |
| 352 // contents from memory. | |
| 353 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) | |
| 354 | |
| 355 // Write dirty cache lines to memory and invalidate the cache entries | |
| 356 // for the given address range. | |
| 2 | 357 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \ |
| 358 CYG_MACRO_START \ | |
| 359 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 360 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 361 while (__size > 0) { \ | |
| 362 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \ | |
| 363 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 364 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 365 } \ | |
| 366 CYG_MACRO_END | |
| 367 | |
| 0 | 368 // Invalidate cache lines in the given range without writing to memory. |
| 2 | 369 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \ |
| 370 CYG_MACRO_START \ | |
| 371 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 372 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 373 while (__size > 0) { \ | |
| 374 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \ | |
| 375 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 376 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 377 } \ | |
| 378 CYG_MACRO_END | |
| 0 | 379 |
| 380 // Write dirty cache lines to memory for the given address range. | |
| 2 | 381 #define HAL_DCACHE_STORE( _base_ , _size_ ) \ |
| 382 CYG_MACRO_START \ | |
| 383 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 384 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 385 while (__size > 0) { \ | |
| 386 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \ | |
| 387 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 388 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 389 } \ | |
| 390 CYG_MACRO_END | |
| 0 | 391 |
| 392 // Preread the given range into the cache with the intention of reading | |
| 393 // from it later. | |
| 2 | 394 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \ |
| 395 CYG_MACRO_START \ | |
| 396 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 397 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 398 while (__size > 0) { \ | |
| 399 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \ | |
| 400 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 401 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 402 } \ | |
| 403 CYG_MACRO_END | |
| 0 | 404 |
| 405 // Preread the given range into the cache with the intention of writing | |
| 406 // to it later. | |
| 2 | 407 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \ |
| 408 CYG_MACRO_START \ | |
| 409 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 410 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 411 while (__size > 0) { \ | |
| 412 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \ | |
| 413 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 414 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 415 } \ | |
| 416 CYG_MACRO_END | |
| 0 | 417 |
| 418 // Allocate and zero the cache lines associated with the given range. | |
| 2 | 419 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \ |
| 420 CYG_MACRO_START \ | |
| 421 cyg_uint32 __base = (cyg_uint32) (_base_); \ | |
| 422 cyg_int32 __size = (cyg_int32) (_size_); \ | |
| 423 while (__size > 0) { \ | |
| 424 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \ | |
| 425 __base += HAL_DCACHE_LINE_SIZE; \ | |
| 426 __size -= HAL_DCACHE_LINE_SIZE; \ | |
| 427 } \ | |
| 428 CYG_MACRO_END | |
| 0 | 429 |
| 430 //----------------------------------------------------------------------------- | |
| 431 // Global control of Instruction cache | |
| 432 | |
| 433 // Enable the instruction cache | |
| 2 | 434 #define HAL_ICACHE_ENABLE() \ |
| 435 asm volatile ("isync;" \ | |
| 436 "mtspr %0, %1;" \ | |
| 437 "isync" \ | |
| 438 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE)) | |
| 0 | 439 |
| 440 // Disable the instruction cache | |
| 2 | 441 #define HAL_ICACHE_DISABLE() \ |
| 442 asm volatile ("isync;" \ | |
| 443 "mtspr %0, %1;" \ | |
| 444 "isync" \ | |
| 445 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD)) | |
| 0 | 446 |
| 447 // Invalidate the entire cache | |
| 2 | 448 #define HAL_ICACHE_INVALIDATE_ALL() \ |
| 449 asm volatile ("isync;" \ | |
| 450 "mtspr %0, %1;" \ | |
| 451 "isync" \ | |
| 452 : : "I" (CYGARC_REG_IC_CST), \ | |
| 453 "r" (CYGARC_REG_IC_CMD_IA)) | |
| 0 | 454 |
| 455 // Synchronize the contents of the cache with memory. | |
| 456 #define HAL_ICACHE_SYNC() | |
| 457 | |
| 2 | 458 // Query the state of the instruction cache |
| 459 #define HAL_ICACHE_IS_ENABLED(_state_) \ | |
| 460 asm volatile ("mfspr %0, %1;" \ | |
| 461 "rlwinm %0,%0,1,31,31;" \ | |
| 462 : "=r" (_state_) : "I" (CYGARC_REG_IC_CST)) | |
| 0 | 463 |
| 464 // Set the instruction cache refill burst size | |
| 465 //#define HAL_ICACHE_BURST_SIZE(_size_) | |
| 466 | |
| 2 | 467 |
| 0 | 468 // Load the contents of the given address range into the instruction cache |
| 469 // and then lock the cache so that it stays there. | |
| 2 | 470 |
| 471 // Restrictions: This implementation only allows a single area to be | |
| 472 // locked at any one time. This area must be 2kB or less in size. | |
| 473 | |
| 474 // Implementation: Flush entire cache, then invalidate it. This | |
| 475 // ensures that the fetched data go into way0. | |
| 476 | |
| 477 #define HAL_ICACHE_LOCK(_base_, _size_) \ | |
| 478 CYG_MACRO_START \ | |
| 479 unsigned long __base = \ | |
| 480 ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \ | |
| 481 int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \ | |
| 482 do { \ | |
| 483 asm volatile ("mtspr %0, %2;" \ | |
| 484 "mtspr %1, %3;" \ | |
| 485 "isync;" \ | |
| 486 : /* no output */ \ | |
| 487 : /* %0 */ "I" (CYGARC_REG_IC_ADR), \ | |
| 488 /* %1 */ "I" (CYGARC_REG_IC_CST), \ | |
| 489 /* %2 */ "r" (__base), \ | |
| 490 /* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \ | |
| 491 __base += HAL_ICACHE_LINE_SIZE; \ | |
| 492 } while (__count--); \ | |
| 493 CYG_MACRO_END | |
| 0 | 494 |
| 495 // Undo a previous lock operation | |
| 2 | 496 |
| 497 // Implementation: Unlocks entire cache. | |
| 498 #define HAL_ICACHE_UNLOCK(_base_, _size_) \ | |
| 499 HAL_ICACHE_UNLOCK_ALL() | |
| 500 | |
| 501 // Unlock entire cache | |
| 502 #define HAL_ICACHE_UNLOCK_ALL() \ | |
| 503 CYG_MACRO_START \ | |
| 504 asm volatile ("sync;" \ | |
| 505 "mtspr %0, %1;" \ | |
| 506 : : "I" (CYGARC_REG_IC_CST), \ | |
| 507 "r" (CYGARC_REG_IC_CMD_UA)); \ | |
| 508 CYG_MACRO_END | |
| 0 | 509 |
| 510 //----------------------------------------------------------------------------- | |
| 511 // Instruction cache line control | |
| 512 | |
| 513 // Invalidate cache lines in the given range without writing to memory. | |
| 514 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) | |
| 515 | |
| 516 #endif | |
| 517 | |
| 518 //----------------------------------------------------------------------------- | |
| 519 #endif // ifndef CYGONCE_HAL_CACHE_H | |
| 520 // End of hal_cache.h |