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annotate packages/hal/arm/edb7xxx/current/src/edb7xxx_misc.c @ 110:84e4bde58b26 ecos-sw-2000-07-14

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Merge from eCos master repository on 2000-07-14-22:00:02-BST
author jlarmour
date Mon, 17 Jul 2000 14:42:27 +0000
parents 435cced73e2f
children 6ed91473a1cd
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1 //==========================================================================
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2 //
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3 // edb7xxx_misc.c
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4 //
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5 // HAL misc board support code for ARM EDB7XXX-1
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Red Hat eCos Public License
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12 // Version 1.1 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://www.redhat.com/
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Configurable Operating System,
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22 // released September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Red Hat.
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25 // Portions created by Red Hat are
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
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27 // All Rights Reserved.
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28 // -------------------------------------------
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29 //
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30 //####COPYRIGHTEND####
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31 //==========================================================================
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32 //#####DESCRIPTIONBEGIN####
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33 //
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34 // Author(s): gthomas
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35 // Contributors: gthomas
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36 // Date: 1999-02-20
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37 // Purpose: HAL board support
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38 // Description: Implementations of HAL board interfaces
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39 //
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40 //####DESCRIPTIONEND####
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41 //
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42 //========================================================================*/
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43
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44 #include <pkgconf/hal.h>
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45 #include <pkgconf/system.h>
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46 #include CYGBLD_HAL_PLATFORM_H
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47
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48 #include <cyg/infra/cyg_type.h> // base types
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49 #include <cyg/infra/cyg_trac.h> // tracing macros
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50 #include <cyg/infra/cyg_ass.h> // assertion macros
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51
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52 #include <cyg/hal/hal_io.h> // IO macros
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53 #include <cyg/hal/hal_arch.h> // Register state info
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54 #include <cyg/hal/hal_diag.h>
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55 #include <cyg/hal/hal_intr.h> // Interrupt names
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56 #include <cyg/hal/hal_cache.h>
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57 #include <cyg/hal/hal_edb7xxx.h> // Hardware definitions
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58 #include <cyg/hal/hal_if.h> // calling interface API
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59
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60 // #define CYGHWR_HAL_ARM_EDB7XXX_BATLOW
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61 #ifdef CYGHWR_HAL_ARM_EDB7XXX_BATLOW
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62 #include <cyg/hal/hal_intr.h> // HAL interrupt macros
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63 #include <cyg/hal/drv_api.h> // HAL ISR support
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64 static cyg_interrupt batlow_interrupt;
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65 static cyg_handle_t batlow_interrupt_handle;
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66 #endif
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67
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68 #if (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK == 18432)
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69 #define CPU_CLOCK 0
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70 #elif (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK == 36864)
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71 #define CPU_CLOCK 1
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72 #elif (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK == 49152)
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73 #define CPU_CLOCK 2
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74 #elif (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK == 73728)
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75 #define CPU_CLOCK 3
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76 #else
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77 #err Invalid CPU clock frequency
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78 #endif
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79
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80 static cyg_uint32 _period;
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81
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82 // Use Timer/Counter #2 for system clock
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83
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84 void hal_clock_initialize(cyg_uint32 period)
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85 {
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86 volatile cyg_uint32 *syscon1 = (volatile cyg_uint32 *)SYSCON1;
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87 volatile cyg_uint32 *tc2d = (volatile cyg_uint32 *)TC2D;
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88 // Set timer to 512KHz, prescale mode
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89 *syscon1 = (*syscon1 & ~(SYSCON1_TC2M|SYSCON1_TC2S)) | SYSCON1_TC2S | SYSCON1_TC2M;
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90 // Initialize counter
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91 *tc2d = period;
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92 _period = period;
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93 }
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94
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95 // This routine is called during a clock interrupt.
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96
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97 static void __inline__
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98 enable_FIQ(void)
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99 {
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100 asm volatile ("mrs r0,cpsr;"
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101 "bic r0,r0,#0x40;"
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102 "msr cpsr,r0");
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103 }
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104
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105 #ifdef CYGHWR_HAL_ARM_EDB7XXX_SOFTWARE_DRAM_REFRESH
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106 #define DRAM_START 0x00000000
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107 #define DRAM_END 0x01000000
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108 #define DRAM_ROW_SIZE 0x00000400
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109 #define DRAM_REFRESH (((DRAM_END-DRAM_START)/DRAM_ROW_SIZE)+99)/100
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110
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111 static void
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112 do_DRAM_refresh(void)
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113 {
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114 static cyg_uint32 *row_ptr;
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115 volatile cyg_uint32 val;
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116 int i;
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117 for (i = 0; i < DRAM_REFRESH; i++) {
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118 val = *row_ptr;
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119 row_ptr += DRAM_ROW_SIZE / sizeof(*row_ptr);
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120 if (row_ptr >= (cyg_uint32 *)DRAM_END) row_ptr = (cyg_uint32 *)DRAM_START;
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121 }
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122 }
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123 #endif // CYGHWR_HAL_ARM_EDB7XXX_SOFTWARE_DRAM_REFRESH
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124
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125 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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126 {
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127 volatile cyg_uint32 *tc2d = (volatile cyg_uint32 *)TC2D;
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128 if (period != _period) {
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129 *tc2d = period;
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130 _period = period;
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131 }
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132 #ifndef CYGPKG_HAL_ARM_EDB7209
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133 // EP7209 has no DRAM/controller, thus no problem
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134 enable_FIQ(); // Should be safe here
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135 #ifdef CYGHWR_HAL_ARM_EDB7XXX_SOFTWARE_DRAM_REFRESH
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136 do_DRAM_refresh();
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137 #else
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138 // Temporary fix for DRAM starvation problem
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139 if (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK > 37000) {
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140 int i;
66
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141 for (i = 0; i < (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK*2)/24; i++) ; // approx 300 us
54
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142 }
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143 #endif
76
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144 #endif
54
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145 }
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146
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147 // Read the current value of the clock, returning the number of hardware "ticks"
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148 // that have occurred (i.e. how far away the current value is from the start)
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149
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150 void hal_clock_read(cyg_uint32 *pvalue)
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151 {
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152 volatile cyg_int32 *tc2d = (volatile cyg_int32 *)TC2D;
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153 static cyg_int32 clock_val;
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154 clock_val = *tc2d & 0x0000FFFF; // Register has only 16 bits
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155 if (clock_val & 0x00008000) clock_val |= 0xFFFF8000; // Extend sign bit
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156 *pvalue = (cyg_uint32)(_period - clock_val); // 'clock_val' counts down and wraps
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157 }
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158
110
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159 void
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160 dram_delay_loop(void)
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161 {
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162 // Temporary fix for DRAM starvation problem
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163 if (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK > 37000) {
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164 int i;
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165 for (i = 0; i < (CYGHWR_HAL_ARM_EDB7XXX_PROCESSOR_CLOCK*2)/24; i++) ; // approx 300 us
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166 }
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167 }
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168
54
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169 // These tables map the various [soft] interrupt numbers onto the hardware
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170
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171 static cyg_uint32 hal_interrupt_bitmap[] = {
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172 0, // CYGNUM_HAL_INTERRUPT_unused 0
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173 INTSR1_EXTFIQ, // CYGNUM_HAL_INTERRUPT_EXTFIQ 1
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174 INTSR1_BLINT, // CYGNUM_HAL_INTERRUPT_BLINT 2
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175 INTSR1_WEINT, // CYGNUM_HAL_INTERRUPT_WEINT 3
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176 INTSR1_MCINT, // CYGNUM_HAL_INTERRUPT_MCINT 4
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177 INTSR1_CSINT, // CYGNUM_HAL_INTERRUPT_CSINT 5
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178 INTSR1_EINT1, // CYGNUM_HAL_INTERRUPT_EINT1 6
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179 INTSR1_EINT2, // CYGNUM_HAL_INTERRUPT_EINT2 7
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180 INTSR1_EINT3, // CYGNUM_HAL_INTERRUPT_EINT3 8
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181 INTSR1_TC1OI, // CYGNUM_HAL_INTERRUPT_TC1OI 9
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182 INTSR1_TC2OI, // CYGNUM_HAL_INTERRUPT_TC2OI 10
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183 INTSR1_RTCMI, // CYGNUM_HAL_INTERRUPT_RTCMI 11
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184 INTSR1_TINT, // CYGNUM_HAL_INTERRUPT_TINT 12
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185 INTSR1_UTXINT1, // CYGNUM_HAL_INTERRUPT_UTXINT1 13
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186 INTSR1_URXINT1, // CYGNUM_HAL_INTERRUPT_URXINT1 14
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187 INTSR1_UMSINT, // CYGNUM_HAL_INTERRUPT_UMSINT 15
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188 INTSR1_SSEOTI, // CYGNUM_HAL_INTERRUPT_SSEOTI 16
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189 INTSR2_KBDINT, // CYGNUM_HAL_INTERRUPT_KBDINT 17
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190 INTSR2_SS2RX, // CYGNUM_HAL_INTERRUPT_SS2RX 18
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191 INTSR2_SS2TX, // CYGNUM_HAL_INTERRUPT_SS2TX 19
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192 INTSR2_UTXINT2, // CYGNUM_HAL_INTERRUPT_UTXINT2 20
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193 INTSR2_URXINT2, // CYGNUM_HAL_INTERRUPT_URXINT2 21
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194 #if defined(__EDB7211)
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195 INTSR3_MCPINT // CYGNUM_HAL_INTERRUPT_MCPINT 22
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196 #endif
76
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197 #if defined(__EDB7209)
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198 INTSR3_I2SINT // CYGNUM_HAL_INTERRUPT_I2SINT 22
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199 #endif
54
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200 };
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201
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202 static cyg_uint32 hal_interrupt_mask_regmap[] = {
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203 0, // CYGNUM_HAL_INTERRUPT_unused 0
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204 INTMR1, // CYGNUM_HAL_INTERRUPT_EXTFIQ 1
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205 INTMR1, // CYGNUM_HAL_INTERRUPT_BLINT 2
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206 INTMR1, // CYGNUM_HAL_INTERRUPT_WEINT 3
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207 INTMR1, // CYGNUM_HAL_INTERRUPT_MCINT 4
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208 INTMR1, // CYGNUM_HAL_INTERRUPT_CSINT 5
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209 INTMR1, // CYGNUM_HAL_INTERRUPT_EINT1 6
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210 INTMR1, // CYGNUM_HAL_INTERRUPT_EINT2 7
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211 INTMR1, // CYGNUM_HAL_INTERRUPT_EINT3 8
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212 INTMR1, // CYGNUM_HAL_INTERRUPT_TC1OI 9
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213 INTMR1, // CYGNUM_HAL_INTERRUPT_TC2OI 10
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214 INTMR1, // CYGNUM_HAL_INTERRUPT_RTCMI 11
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215 INTMR1, // CYGNUM_HAL_INTERRUPT_TINT 12
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216 INTMR1, // CYGNUM_HAL_INTERRUPT_UTXINT1 13
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217 INTMR1, // CYGNUM_HAL_INTERRUPT_URXINT1 14
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218 INTMR1, // CYGNUM_HAL_INTERRUPT_UMSINT 15
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219 INTMR1, // CYGNUM_HAL_INTERRUPT_SSEOTI 16
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220 INTMR2, // CYGNUM_HAL_INTERRUPT_KBDINT 17
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221 INTMR2, // CYGNUM_HAL_INTERRUPT_SS2RX 18
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222 INTMR2, // CYGNUM_HAL_INTERRUPT_SS2TX 19
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223 INTMR2, // CYGNUM_HAL_INTERRUPT_UTXINT2 20
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224 INTMR2, // CYGNUM_HAL_INTERRUPT_URXINT2 21
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225 #if defined(__EDB7211)
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226 INTMR3, // CYGNUM_HAL_INTERRUPT_MCPINT 22
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227 #endif
76
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228 #if defined(__EDB7209)
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229 INTMR3, // CYGNUM_HAL_INTERRUPT_I2SINT 22
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230 #endif
54
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231 };
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232
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233 static cyg_uint32 hal_interrupt_clear_map[] = {
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234 0, // CYGNUM_HAL_INTERRUPT_unused 0
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235 0, // CYGNUM_HAL_INTERRUPT_EXTFIQ 1
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236 BLEOI, // CYGNUM_HAL_INTERRUPT_BLINT 2
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237 TEOI, // CYGNUM_HAL_INTERRUPT_WEINT 3
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238 MCEOI, // CYGNUM_HAL_INTERRUPT_MCINT 4
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239 COEOI, // CYGNUM_HAL_INTERRUPT_CSINT 5
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240 0, // CYGNUM_HAL_INTERRUPT_EINT1 6
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241 0, // CYGNUM_HAL_INTERRUPT_EINT2 7
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242 0, // CYGNUM_HAL_INTERRUPT_EINT3 8
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243 TC1EOI, // CYGNUM_HAL_INTERRUPT_TC1OI 9
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244 TC2EOI, // CYGNUM_HAL_INTERRUPT_TC2OI 10
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245 RTCEOI, // CYGNUM_HAL_INTERRUPT_RTCMI 11
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246 TEOI, // CYGNUM_HAL_INTERRUPT_TINT 12
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247 0, // CYGNUM_HAL_INTERRUPT_UTXINT1 13
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248 0, // CYGNUM_HAL_INTERRUPT_URXINT1 14
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249 UMSEOI, // CYGNUM_HAL_INTERRUPT_UMSINT 15
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250 0, // CYGNUM_HAL_INTERRUPT_SSEOTI 16
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251 KBDEOI, // CYGNUM_HAL_INTERRUPT_KBDINT 17
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252 0, // CYGNUM_HAL_INTERRUPT_SS2RX 18
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253 0, // CYGNUM_HAL_INTERRUPT_SS2TX 19
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254 0, // CYGNUM_HAL_INTERRUPT_UTXINT2 20
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255 0, // CYGNUM_HAL_INTERRUPT_URXINT2 21
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256 #if defined(__EDB7211)
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257 0, // CYGNUM_HAL_INTERRUPT_MCPINT 22
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258 #endif
76
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259 #if defined(__EDB7209)
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260 0, // CYGNUM_HAL_INTERRUPT_I2SINT 22
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261 #endif
54
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262 };
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263
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264 static struct regmap {
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265 int first_int, last_int;
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266 cyg_uint32 stat_reg, mask_reg;
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267 } hal_interrupt_status_regmap[] = {
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268 { CYGNUM_HAL_INTERRUPT_EXTFIQ, CYGNUM_HAL_INTERRUPT_SSEOTI, INTSR1, INTMR1},
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269 { CYGNUM_HAL_INTERRUPT_KBDINT, CYGNUM_HAL_INTERRUPT_URXINT2, INTSR2, INTMR2},
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270 #if defined(__EDB7211)
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271 { CYGNUM_HAL_INTERRUPT_MCPINT, CYGNUM_HAL_INTERRUPT_MCPINT, INTSR3, INTMR3},
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272 #endif
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273 #if defined(__EDB7209)
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274 { CYGNUM_HAL_INTERRUPT_I2SINT, CYGNUM_HAL_INTERRUPT_I2SINT, INTSR3, INTMR3},
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275 #endif
54
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276 { 0, 0, 0}
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277 };
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278
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279 #ifdef CYGHWR_HAL_ARM_EDB7XXX_BATLOW
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280 // This ISR is called when the battery low interrupt occurs
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281 int
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282 cyg_hal_batlow_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
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283 {
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284 diag_printf("Battery low\n");
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285 cyg_drv_interrupt_mask(CYGNUM_HAL_INTERRUPT_BLINT);
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286 // Presumably, one would leave this masked until the battery changed
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287 cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_BLINT);
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288 return 0; // No need to run DSR
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289 }
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290 #endif
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291
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292 //
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293 // Early stage hardware initialization
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294 // Some initialization has already been done before we get here. For now
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295 // just set up the interrupt environment.
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296
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297 void hal_hardware_init(void)
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298 {
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299 volatile cyg_uint32 *icr;
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300 int vector;
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301 // Clear and initialize instruction cache
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302 HAL_ICACHE_INVALIDATE_ALL();
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303 HAL_ICACHE_ENABLE();
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304 // Any hardware/platform initialization that needs to be done.
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305 *(volatile cyg_uint32 *)INTMR1 = 0;
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306 *(volatile cyg_uint32 *)INTMR2 = 0;
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307 #if !defined(__CL7111)
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308 *(volatile cyg_uint32 *)INTMR3 = 0;
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309 *(volatile cyg_uint8 *)SYSCON3 = SYSCON3_CLKCTL(CPU_CLOCK);
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310 #endif
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311 #if 0
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312 diag_printf("IMR1: %04x, IMR2: %04x\n",
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313 *(volatile cyg_uint32 *)INTMR1,
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314 *(volatile cyg_uint32 *)INTMR2);
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315 diag_printf("Memcfg1: %08x, Memcfg2: %08x, DRAM refresh: %08x\n",
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316 *(volatile cyg_uint32 *)MEMCFG1,
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317 *(volatile cyg_uint32 *)MEMCFG2,
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318 *(volatile cyg_uint8 *)DRFPR);
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319 #endif
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320 #define MEMCFG_BUS_WIDTH(n) (n<<0)
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321 #define MEMCFG_BUS_WIDTH_32 (0<<0)
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322 #define MEMCFG_BUS_WIDTH_16 (1<<0)
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323 #define MEMCFG_BUS_WIDTH_8 (2<<0)
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324 #define MEMCFG_WAIT_STATES(n) (n<<2) // 0 is max, 15 min
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325 #define MEMCFG_SQAEN (1<<6)
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326 #define MEMCFG_CLKENB (1<<7)
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327
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328 // These need to be checked/improved
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329 #define CS0_CONFIG MEMCFG_BUS_WIDTH_32 | MEMCFG_WAIT_STATES(3) | MEMCFG_SQAEN
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330 #define CS1_CONFIG MEMCFG_BUS_WIDTH_32 | MEMCFG_WAIT_STATES(4)
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331 #define CS2_CONFIG MEMCFG_BUS_WIDTH_32 | MEMCFG_WAIT_STATES(0)
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332 #define CS3_CONFIG MEMCFG_BUS_WIDTH_32 | MEMCFG_WAIT_STATES(0)
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333 #define CS4_CONFIG MEMCFG_BUS_WIDTH_32 | MEMCFG_WAIT_STATES(0)
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334 #define CS5_CONFIG MEMCFG_BUS_WIDTH_32 | MEMCFG_WAIT_STATES(0)
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335 #define CS6_CONFIG MEMCFG_BUS_WIDTH_32 | MEMCFG_WAIT_STATES(0)
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336 #define CS7_CONFIG MEMCFG_BUS_WIDTH_32 | MEMCFG_WAIT_STATES(0)
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337
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338 #if defined(__EDB7209)
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339 *(volatile cyg_uint32 *)MEMCFG1 =
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340 (CS0_CONFIG << 0) | // FLASH rom
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341 (CS1_CONFIG << 8) | // NAND flash
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342 (CS2_CONFIG << 16) | // Ethernet
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343 (CS3_CONFIG << 24); // Parallel printer, keyboard, touch panel
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344 *(volatile cyg_uint32 *)MEMCFG2 =
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345 (CS4_CONFIG << 0) | // USB
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346 (CS5_CONFIG << 8) | // Expansion
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347 (CS6_CONFIG << 16) | // Local SRAM
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348 (CS7_CONFIG << 24); // Boot ROM
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349 // This value came from Cirrus, but doesn't match the recommendations above?
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350 *(volatile cyg_uint32 *)MEMCFG1 = 0x3C001814;
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351 // Set up GPIO lines
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352 *(volatile cyg_uint8 *)PADDR = 0x00; // Keyboard data 0-7 input
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353 *(volatile cyg_uint8 *)PBDDR = 0xFA; // 0 - I/O on J22
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354 // 1 - RTS on UART1
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355 // 2 - Ring on UART1
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356 // 3 - SSI header, Pin 13
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357 // 4 - NAND Command Latch Enable
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358 // 5 - NAND Address Latch Enable
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359 // 6 - On-board NAND Select (active low)
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360 // 7 - SmartMedia Card Enable (active low)
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361 *(volatile cyg_uint8 *)PBDR = 0xC0; // Everything off
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362 *(volatile cyg_uint8 *)PDDDR = 0x40; // 0 - Diagnostic LED control
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363 // 1 - Enable DC-DC converter for LCD
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364 // 2 - Enable LCD
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365 // 3 - ENable LCD Backlight
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366 // 4 - CS4342 I2C Data
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367 // 5 - CS4342 I2C Clock
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368 // 6 - SmartMedia Presence indicator
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369 // 7 - I/O on J22
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370 *(volatile cyg_uint8 *)PDDR = 0x00; // Everything off
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371 *(volatile cyg_uint8 *)PEDDR = 0x05; // 0 - Codec or ADC/DAC
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372 // 1 - I/O on JP38 (0 when inserted)
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373 // 2 - Enable touch panel
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374 *(volatile cyg_uint8 *)PEDR = 0x01; // Enable audio (not CODEC)
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375 // Initialize system control
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376 *(volatile cyg_uint32 *)SYSCON2 = SYSCON2_KBWEN;
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377 #endif
54
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378 // Reset all interrupt masks (disable all interrupt sources)
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379 for (vector = CYGNUM_HAL_ISR_MIN; vector < CYGNUM_HAL_ISR_COUNT; vector++) {
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380 icr = (volatile cyg_uint32 *)hal_interrupt_clear_map[vector];
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381 if (icr) *icr = 0; // Just a write clears the latch
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382 }
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383 // Turn on the DIAG LED to let the world know the board is alive
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384 *(volatile unsigned char *)LEDFLSH = LEDFLSH_ENABLE|LEDFLSH_DUTY(16)|LEDFLSH_PERIOD(1);
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385 #ifdef CYGHWR_HAL_ARM_EDB7XXX_BATLOW
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386 cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_BLINT,
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387 99, // Priority - what goes here?
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388 0, // Data item passed to interrupt handler
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389 cyg_hal_batlow_isr,
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390 0,
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391 &batlow_interrupt_handle,
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392 &batlow_interrupt);
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393 cyg_drv_interrupt_attach(batlow_interrupt_handle);
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394 cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_BLINT);
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395 #endif
110
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396
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397 // Set up eCos/ROM interfaces
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398 hal_if_init();
54
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399 }
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400
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401 //
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402 // This routine is called to respond to a hardware interrupt (IRQ). It
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403 // should interrogate the hardware and return the IRQ vector number.
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404
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405 // This code is a little convoluted to keep it general while still avoiding
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406 // reading the hardware a lot, since the interrupt status is split across
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407 // three separate registers.
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408
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409 int hal_spurious_ints;
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410
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411 int hal_IRQ_handler(void)
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412 {
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413 struct regmap *map = hal_interrupt_status_regmap;
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414 cyg_uint32 stat;
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415 int vector;
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416 while (map->first_int) {
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417 stat = *(volatile cyg_uint32 *)map->stat_reg & *(volatile cyg_uint32 *)map->mask_reg;
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418 for (vector = map->first_int; vector <= map->last_int; vector++) {
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419 if (stat & hal_interrupt_bitmap[vector]) return vector;
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420 }
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421 map++; // Next interrupt status register
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422 }
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423 hal_spurious_ints++;
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424 return CYGNUM_HAL_INTERRUPT_unused; // This shouldn't happen!
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425 }
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426
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427 //
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428 // Interrupt control
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429 //
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430
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431 void hal_interrupt_mask(int vector)
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432 {
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433 volatile cyg_uint32 *imr;
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434 imr = (volatile cyg_uint32 *)hal_interrupt_mask_regmap[vector];
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435 *imr &= ~hal_interrupt_bitmap[vector];
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436 }
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437
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438 void hal_interrupt_unmask(int vector)
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439 {
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440 volatile cyg_uint32 *imr;
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441 imr = (volatile cyg_uint32 *)hal_interrupt_mask_regmap[vector];
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442 *imr |= hal_interrupt_bitmap[vector];
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443 }
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444
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445 void hal_interrupt_acknowledge(int vector)
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446 {
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447 // Some interrupt sources have a register for this.
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448 volatile cyg_uint8 *icr;
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449 icr = (volatile cyg_uint8 *)hal_interrupt_clear_map[vector];
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450 if (icr) {
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451 *icr = 0; // Any data clears interrupt
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452 }
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453 }
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454
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455 void hal_interrupt_configure(int vector, int level, int up)
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456 {
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457 // No interrupts are configurable on this hardware
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458 }
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459
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460 void hal_interrupt_set_level(int vector, int level)
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461 {
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462 // No interrupts are configurable on this hardware
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463 }
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464
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465 /*------------------------------------------------------------------------*/
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466 // EOF hal_misc.c