Mercurial > ecos
annotate packages/hal/mips/arch/current/include/hal_intr.h @ 92:08ffab08d2ee ecos-sw-2000-05-26
Merge from eCos master repository on 2000-05-26-07:47:03-BST
| author | jlarmour |
|---|---|
| date | Fri, 26 May 2000 13:46:34 +0000 |
| parents | 70190fa0fe10 |
| children | 02ea4320376c |
| rev | line source |
|---|---|
| 0 | 1 #ifndef CYGONCE_HAL_HAL_INTR_H |
| 2 #define CYGONCE_HAL_HAL_INTR_H | |
| 3 | |
| 2 | 4 //========================================================================== |
| 0 | 5 // |
| 2 | 6 // hal_intr.h |
| 0 | 7 // |
| 2 | 8 // HAL Interrupt and clock support |
| 0 | 9 // |
| 2 | 10 //========================================================================== |
| 0 | 11 //####COPYRIGHTBEGIN#### |
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12 // |
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13 // ------------------------------------------- |
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14 // The contents of this file are subject to the Red Hat eCos Public License |
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15 // Version 1.1 (the "License"); you may not use this file except in |
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16 // compliance with the License. You may obtain a copy of the License at |
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17 // http://www.redhat.com/ |
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18 // |
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19 // Software distributed under the License is distributed on an "AS IS" |
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20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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21 // License for the specific language governing rights and limitations under |
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22 // the License. |
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23 // |
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24 // The Original Code is eCos - Embedded Configurable Operating System, |
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25 // released September 30, 1998. |
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26 // |
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27 // The Initial Developer of the Original Code is Red Hat. |
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28 // Portions created by Red Hat are |
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29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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30 // All Rights Reserved. |
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31 // ------------------------------------------- |
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32 // |
| 0 | 33 //####COPYRIGHTEND#### |
| 2 | 34 //========================================================================== |
| 0 | 35 //#####DESCRIPTIONBEGIN#### |
| 36 // | |
| 2 | 37 // Author(s): nickg |
| 38 // Contributors: nickg, jskov, | |
| 39 // gthomas, jlarmour | |
| 40 // Date: 1999-02-16 | |
| 41 // Purpose: Define Interrupt support | |
| 42 // Description: The macros defined here provide the HAL APIs for handling | |
| 43 // interrupts and the clock. | |
| 0 | 44 // |
| 45 // Usage: | |
| 2 | 46 // #include <cyg/hal/hal_intr.h> |
| 47 // ... | |
| 48 // | |
| 0 | 49 // |
| 50 //####DESCRIPTIONEND#### | |
| 51 // | |
| 2 | 52 //========================================================================== |
| 0 | 53 |
| 54 #include <pkgconf/hal.h> | |
| 55 | |
| 56 #include <cyg/infra/cyg_type.h> | |
| 57 #include <cyg/hal/hal_io.h> | |
| 58 | |
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59 #include <cyg/hal/var_intr.h> |
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60 |
| 2 | 61 //-------------------------------------------------------------------------- |
| 62 // MIPS vectors. | |
| 0 | 63 |
| 2 | 64 // These are the exception codes presented in the Cause register and |
| 65 // correspond to VSRs. These values are the ones to use for HAL_VSR_GET/SET | |
| 0 | 66 |
| 2 | 67 // External interrupt |
| 68 #define CYGNUM_HAL_VECTOR_INTERRUPT 0 | |
| 69 // TLB modification exception | |
| 70 #define CYGNUM_HAL_VECTOR_TLB_MOD 1 | |
| 71 // TLB miss (Load or IFetch) | |
| 72 #define CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL 2 | |
| 73 // TLB miss (Store) | |
| 74 #define CYGNUM_HAL_VECTOR_TLB_STORE_REFILL 3 | |
| 75 // Address error (Load or Ifetch) | |
| 76 #define CYGNUM_HAL_VECTOR_LOAD_ADDRESS 4 | |
| 77 // Address error (store) | |
| 78 #define CYGNUM_HAL_VECTOR_STORE_ADDRESS 5 | |
| 79 // Bus error (Ifetch) | |
| 80 #define CYGNUM_HAL_VECTOR_IBE 6 | |
| 81 // Bus error (data load or store) | |
| 82 #define CYGNUM_HAL_VECTOR_DBE 7 | |
| 83 // System call | |
| 84 #define CYGNUM_HAL_VECTOR_SYSTEM_CALL 8 | |
| 85 // Break point | |
| 86 #define CYGNUM_HAL_VECTOR_BREAKPOINT 9 | |
| 87 // Reserved instruction | |
| 88 #define CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION 10 | |
| 89 // Coprocessor unusable | |
| 90 #define CYGNUM_HAL_VECTOR_COPROCESSOR 11 | |
| 91 // Arithmetic overflow | |
| 92 #define CYGNUM_HAL_VECTOR_OVERFLOW 12 | |
| 93 // Reserved | |
| 94 #define CYGNUM_HAL_VECTOR_RESERVED_13 13 | |
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95 // Division-by-zero [reserved vector] |
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96 // This is caused by 'trap 0x7' which GCC puts in the code to check |
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97 // for division by zero. The break_vsr_springboard in vectors.S is the |
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98 // only caller of this vector. |
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99 #define CYGNUM_HAL_VECTOR_DIV_BY_ZERO 14 |
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100 // Floating point exception |
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101 #ifdef CYGHWR_HAL_MIPS_FPU |
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102 #define CYGNUM_HAL_VECTOR_FPE 15 |
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103 #endif |
| 0 | 104 |
| 2 | 105 #define CYGNUM_HAL_VSR_MIN 0 |
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106 #define CYGNUM_HAL_VSR_MAX 15 |
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107 #define CYGNUM_HAL_VSR_COUNT 16 |
| 2 | 108 |
| 109 // Exception vectors. These are the values used when passed out to an | |
| 110 // external exception handler using cyg_hal_deliver_exception() | |
| 0 | 111 |
| 2 | 112 #define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_TLB_MOD |
| 113 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_ACCESS \ | |
| 114 CYGNUM_HAL_VECTOR_TLB_LOAD_REFILL | |
| 115 #define CYGNUM_HAL_EXCEPTION_DATA_TLBMISS_WRITE \ | |
| 116 CYGNUM_HAL_VECTOR_TLB_STORE_REFILL | |
| 117 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \ | |
| 118 CYGNUM_HAL_VECTOR_LOAD_ADDRESS | |
| 119 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_WRITE \ | |
| 120 CYGNUM_HAL_VECTOR_STORE_ADDRESS | |
| 121 #define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_IBE | |
| 122 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DBE | |
| 123 #define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL | |
| 124 #define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_BREAKPOINT | |
| 125 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \ | |
| 126 CYGNUM_HAL_VECTOR_RESERVED_INSTRUCTION | |
| 127 #define CYGNUM_HAL_EXCEPTION_COPROCESSOR CYGNUM_HAL_VECTOR_COPROCESSOR | |
| 128 #define CYGNUM_HAL_EXCEPTION_OVERFLOW CYGNUM_HAL_VECTOR_OVERFLOW | |
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129 #define CYGNUM_HAL_EXCEPTION_DIV_BY_ZERO CYGNUM_HAL_VECTOR_DIV_BY_ZERO |
| 2 | 130 |
| 131 // Min/Max exception numbers and how many there are | |
| 132 #define CYGNUM_HAL_EXCEPTION_MIN 1 | |
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133 #define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VSR_MAX |
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134 #define CYGNUM_HAL_EXCEPTION_COUNT CYGNUM_HAL_VSR_MAX |
| 0 | 135 |
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136 |
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137 #ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED |
| 0 | 138 |
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139 // the default for all MIPS variants is to use the 6 bits |
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140 // in the cause register. |
| 0 | 141 |
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142 #define CYGNUM_HAL_INTERRUPT_0 0 |
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143 #define CYGNUM_HAL_INTERRUPT_1 1 |
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144 #define CYGNUM_HAL_INTERRUPT_2 2 |
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145 #define CYGNUM_HAL_INTERRUPT_3 3 |
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146 #define CYGNUM_HAL_INTERRUPT_4 4 |
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147 #define CYGNUM_HAL_INTERRUPT_5 5 |
| 0 | 148 |
| 2 | 149 // Min/Max ISR numbers and how many there are |
| 150 #define CYGNUM_HAL_ISR_MIN 0 | |
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151 #define CYGNUM_HAL_ISR_MAX 5 |
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152 #define CYGNUM_HAL_ISR_COUNT 6 |
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154 // The vector used by the Real time clock. The default here is to use |
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155 // interrupt 5, which is connected to the counter/comparator registers |
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156 // in many MIPS variants. |
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157 |
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158 #ifndef CYGNUM_HAL_INTERRUPT_RTC |
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159 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_5 |
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160 #endif |
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161 |
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162 #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED |
| 0 | 163 |
| 164 #endif | |
| 165 | |
| 2 | 166 //-------------------------------------------------------------------------- |
| 0 | 167 // Static data used by HAL |
| 168 | |
| 169 // ISR tables | |
| 2 | 170 externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; |
| 171 externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; | |
| 172 externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; | |
| 0 | 173 |
| 174 // VSR table | |
| 2 | 175 externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_MAX+1]; |
| 0 | 176 |
| 2 | 177 //-------------------------------------------------------------------------- |
| 0 | 178 // Default ISR |
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179 // The #define is used to test whether this routine exists, and to allow |
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180 // us to call it. |
| 0 | 181 |
| 182 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); | |
| 183 | |
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184 #define HAL_DEFAULT_ISR hal_default_isr |
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185 |
| 2 | 186 //-------------------------------------------------------------------------- |
| 0 | 187 // Interrupt state storage |
| 188 | |
| 189 typedef cyg_uint32 CYG_INTERRUPT_STATE; | |
| 190 | |
| 2 | 191 //-------------------------------------------------------------------------- |
| 0 | 192 // Interrupt control macros |
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193 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards |
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194 // that might otherwise cause following code to run in the wrong state or |
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195 // cause a resource conflict. |
| 0 | 196 |
| 197 #define HAL_DISABLE_INTERRUPTS(_old_) \ | |
| 198 { \ | |
| 199 asm volatile ( \ | |
| 200 "mfc0 $8,$12; nop;" \ | |
| 201 "move %0,$8;" \ | |
| 202 "and $8,$8,0XFFFFFFFE;" \ | |
| 203 "mtc0 $8,$12;" \ | |
| 204 "nop; nop; nop;" \ | |
| 205 "and %0,%0,0X1;" \ | |
| 206 : "=r"(_old_) \ | |
| 207 : \ | |
| 208 : "$8" \ | |
| 209 ); \ | |
| 210 } | |
| 211 | |
| 212 #define HAL_ENABLE_INTERRUPTS() \ | |
| 213 { \ | |
| 214 asm volatile ( \ | |
| 215 "mfc0 $8,$12; nop;" \ | |
| 216 "or $8,$8,1;" \ | |
| 217 "mtc0 $8,$12;" \ | |
| 218 "nop; nop; nop;" \ | |
| 219 : \ | |
| 220 : \ | |
| 221 : "$8" \ | |
| 222 ); \ | |
| 223 } | |
| 224 | |
| 225 #define HAL_RESTORE_INTERRUPTS(_old_) \ | |
| 226 { \ | |
| 227 asm volatile ( \ | |
| 228 "mfc0 $8,$12; nop;" \ | |
| 229 "and %0,%0,0x1;" \ | |
| 230 "or $8,$8,%0;" \ | |
| 231 "mtc0 $8,$12;" \ | |
| 232 "nop; nop; nop;" \ | |
| 233 : \ | |
| 234 : "r"(_old_) \ | |
| 235 : "$8" \ | |
| 236 ); \ | |
| 237 } | |
| 238 | |
| 239 #define HAL_QUERY_INTERRUPTS( _state_ ) \ | |
| 240 { \ | |
| 241 asm volatile ( \ | |
| 242 "mfc0 %0,$12; nop;" \ | |
| 243 "and %0,%0,0x1;" \ | |
| 244 : "=r"(_state_) \ | |
| 245 : \ | |
| 246 : "$8" \ | |
| 247 ); \ | |
| 248 } | |
| 249 | |
| 2 | 250 //-------------------------------------------------------------------------- |
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251 // Routine to execute DSRs using separate interrupt stack |
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252 |
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253 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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254 externC void hal_interrupt_stack_call_pending_DSRs(void); |
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255 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ |
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256 hal_interrupt_stack_call_pending_DSRs() |
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257 |
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258 // these are offered solely for stack usage testing |
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259 // if they are not defined, then there is no interrupt stack. |
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260 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base |
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261 #define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack |
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262 // use them to declare these extern however you want: |
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263 // extern char HAL_INTERRUPT_STACK_BASE[]; |
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264 // extern char HAL_INTERRUPT_STACK_TOP[]; |
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265 // is recommended |
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266 #endif |
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267 |
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268 //-------------------------------------------------------------------------- |
| 0 | 269 // Vector translation. |
| 270 // For chained interrupts we only have a single vector though which all | |
| 271 // are passed. For unchained interrupts we have a vector per interrupt. | |
| 272 | |
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273 #ifndef HAL_TRANSLATE_VECTOR |
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274 |
| 0 | 275 #if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) |
| 276 | |
| 277 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0 | |
| 278 | |
| 279 #else | |
| 280 | |
| 281 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_) | |
| 282 | |
| 283 #endif | |
| 284 | |
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285 #endif |
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286 |
| 2 | 287 //-------------------------------------------------------------------------- |
| 0 | 288 // Interrupt and VSR attachment macros |
| 289 | |
| 2 | 290 #define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ |
| 291 CYG_MACRO_START \ | |
| 292 cyg_uint32 _index_; \ | |
| 293 HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ | |
| 294 \ | |
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295 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ |
| 2 | 296 (_state_) = 0; \ |
| 297 else \ | |
| 298 (_state_) = 1; \ | |
| 299 CYG_MACRO_END | |
| 300 | |
| 301 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ | |
| 302 { \ | |
| 303 cyg_uint32 _index_; \ | |
| 304 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ | |
| 305 \ | |
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306 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ |
| 2 | 307 { \ |
| 308 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ | |
| 309 hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ | |
| 310 hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ | |
| 311 } \ | |
| 0 | 312 } |
| 313 | |
| 314 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ | |
| 315 { \ | |
| 316 cyg_uint32 _index_; \ | |
| 317 HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \ | |
| 318 \ | |
| 319 if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ | |
| 320 { \ | |
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321 hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \ |
| 0 | 322 hal_interrupt_data[_index_] = 0; \ |
| 323 hal_interrupt_objects[_index_] = 0; \ | |
| 324 } \ | |
| 325 } | |
| 326 | |
| 327 #define HAL_VSR_GET( _vector_, _pvsr_ ) \ | |
| 328 *(_pvsr_) = (void (*)())hal_vsr_table[_vector_]; | |
| 329 | |
| 330 | |
| 2 | 331 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \ |
| 332 if( _poldvsr_ != NULL) \ | |
| 333 *(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \ | |
| 334 hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \ | |
| 335 CYG_MACRO_END | |
| 336 | |
| 337 // This is an ugly name, but what it means is: grab the VSR back to eCos | |
| 338 // internal handling, or if you like, the default handler. But if | |
| 339 // cooperating with GDB and CygMon, the default behaviour is to pass most | |
| 340 // exceptions to CygMon. This macro undoes that so that eCos handles the | |
| 341 // exception. So use it with care. | |
| 0 | 342 |
| 2 | 343 externC void __default_exception_vsr(void); |
| 344 externC void __default_interrupt_vsr(void); | |
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345 externC void __break_vsr_springboard(void); |
| 2 | 346 |
| 347 #define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \ | |
| 348 HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \ | |
| 349 ? (CYG_ADDRESS)__default_interrupt_vsr \ | |
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350 : _vector_ == CYGNUM_HAL_VECTOR_BREAKPOINT \ |
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351 ? (CYG_ADDRESS)__break_vsr_springboard \ |
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352 : (CYG_ADDRESS)__default_exception_vsr, \ |
| 2 | 353 _poldvsr_ ); \ |
| 354 CYG_MACRO_END | |
| 355 | |
| 356 //-------------------------------------------------------------------------- | |
| 0 | 357 // Interrupt controller access |
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358 // The default code here simply uses the fields present in the CP0 status |
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359 // and cause registers to implement this functionality. |
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360 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards |
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361 // that might otherwise cause following code to run in the wrong state or |
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362 // cause a resource conflict. |
| 0 | 363 |
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364 #ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED |
| 0 | 365 |
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366 #define HAL_INTERRUPT_MASK( _vector_ ) \ |
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367 CYG_MACRO_START \ |
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368 asm volatile ( \ |
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369 "mfc0 $3,$12\n" \ |
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370 "la $2,0x00000400\n" \ |
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371 "sllv $2,$2,%0\n" \ |
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372 "nor $2,$2,$0\n" \ |
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373 "and $3,$3,$2\n" \ |
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374 "mtc0 $3,$12\n" \ |
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375 "nop; nop; nop\n" \ |
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376 : \ |
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377 : "r"(_vector_) \ |
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378 : "$2", "$3" \ |
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379 ); \ |
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380 CYG_MACRO_END |
| 0 | 381 |
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382 #define HAL_INTERRUPT_UNMASK( _vector_ ) \ |
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383 CYG_MACRO_START \ |
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384 asm volatile ( \ |
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385 "mfc0 $3,$12\n" \ |
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386 "la $2,0x00000400\n" \ |
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387 "sllv $2,$2,%0\n" \ |
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388 "or $3,$3,$2\n" \ |
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389 "mtc0 $3,$12\n" \ |
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390 "nop; nop; nop\n" \ |
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391 : \ |
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392 : "r"(_vector_) \ |
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393 : "$2", "$3" \ |
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394 ); \ |
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395 CYG_MACRO_END |
| 0 | 396 |
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397 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ |
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398 CYG_MACRO_START \ |
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399 asm volatile ( \ |
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400 "mfc0 $3,$13\n" \ |
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401 "la $2,0x00000400\n" \ |
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402 "sllv $2,$2,%0\n" \ |
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403 "nor $2,$2,$0\n" \ |
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404 "and $3,$3,$2\n" \ |
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405 "mtc0 $3,$13\n" \ |
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406 "nop; nop; nop\n" \ |
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407 : \ |
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408 : "r"(_vector_) \ |
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409 : "$2", "$3" \ |
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410 ); \ |
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411 CYG_MACRO_END |
| 0 | 412 |
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413 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) |
| 0 | 414 |
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415 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) |
| 0 | 416 |
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417 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED |
| 0 | 418 |
| 419 #endif | |
| 420 | |
| 2 | 421 //-------------------------------------------------------------------------- |
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422 // Clock control. |
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423 // This code uses the count and compare registers that are present in many |
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424 // MIPS variants. |
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425 // Beware of nops in this code. They fill delay slots and avoid CP0 hazards |
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426 // that might otherwise cause following code to run in the wrong state or |
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427 // cause a resource conflict. |
| 0 | 428 |
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429 #ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED |
| 2 | 430 |
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431 externC CYG_WORD32 cyg_hal_clock_period; |
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432 #define CYGHWR_HAL_CLOCK_PERIOD_DEFINED |
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433 |
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434 #define HAL_CLOCK_INITIALIZE( _period_ ) \ |
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435 CYG_MACRO_START \ |
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436 asm volatile ( \ |
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437 "mtc0 $0,$9\n" \ |
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438 "nop; nop; nop\n" \ |
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439 "mtc0 %0,$11\n" \ |
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440 "nop; nop; nop\n" \ |
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441 : \ |
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442 : "r"(_period_) \ |
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443 ); \ |
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444 cyg_hal_clock_period = _period_; \ |
| 2 | 445 CYG_MACRO_END |
| 446 | |
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447 #define HAL_CLOCK_RESET( _vector_, _period_ ) \ |
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448 CYG_MACRO_START \ |
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449 asm volatile ( \ |
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450 "mtc0 $0,$9\n" \ |
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451 "nop; nop; nop\n" \ |
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452 "mtc0 %0,$11\n" \ |
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453 "nop; nop; nop\n" \ |
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454 : \ |
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455 : "r"(_period_) \ |
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456 ); \ |
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457 CYG_MACRO_END |
| 2 | 458 |
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459 #define HAL_CLOCK_READ( _pvalue_ ) \ |
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460 CYG_MACRO_START \ |
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461 register CYG_WORD32 result; \ |
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462 asm volatile ( \ |
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463 "mfc0 %0,$9\n" \ |
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464 : "=r"(result) \ |
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465 ); \ |
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466 *(_pvalue_) = result; \ |
| 2 | 467 CYG_MACRO_END |
| 468 | |
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469 #define CYGHWR_HAL_CLOCK_CONTROL_DEFINED |
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470 |
| 2 | 471 #endif |
| 472 | |
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473 #if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \ |
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474 !defined(HAL_CLOCK_LATENCY) |
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475 #define HAL_CLOCK_LATENCY( _pvalue_ ) \ |
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476 CYG_MACRO_START \ |
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477 register CYG_WORD32 _cval_; \ |
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478 HAL_CLOCK_READ(&_cval_); \ |
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479 *(_pvalue_) = _cval_ - cyg_hal_clock_period; \ |
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480 CYG_MACRO_END |
| 2 | 481 #endif |
| 0 | 482 |
| 2 | 483 //-------------------------------------------------------------------------- |
| 0 | 484 #endif // ifndef CYGONCE_HAL_HAL_INTR_H |
| 485 // End of hal_intr.h |
