Mercurial > ecos
annotate packages/hal/mips/arch/current/src/vectors.S @ 16:4f2df4ab82c8 ecos-sw-1999-06-18
Merge from eCos master repository on 1999-06-18-15:25:04-BST
| author | jlarmour |
|---|---|
| date | Fri, 18 Jun 1999 07:59:09 +0000 |
| parents | 01ce82f3e11a |
| children | 306eee292492 |
| rev | line source |
|---|---|
| 0 | 1 ##============================================================================= |
| 2 ## | |
| 3 ## vectors.S | |
| 4 ## | |
| 5 ## MIPS exception vectors | |
| 6 ## | |
| 7 ##============================================================================= | |
| 8 #####COPYRIGHTBEGIN#### | |
| 9 # | |
| 10 # ------------------------------------------- | |
| 11 # The contents of this file are subject to the Cygnus eCos Public License | |
| 12 # Version 1.0 (the "License"); you may not use this file except in | |
| 13 # compliance with the License. You may obtain a copy of the License at | |
| 14 # http://sourceware.cygnus.com/ecos | |
| 15 # | |
| 16 # Software distributed under the License is distributed on an "AS IS" | |
| 17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 # License for the specific language governing rights and limitations under | |
| 19 # the License. | |
| 20 # | |
| 21 # The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 # September 30, 1998. | |
| 23 # | |
| 24 # The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 25 # by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 26 # ------------------------------------------- |
| 27 # | |
| 28 #####COPYRIGHTEND#### | |
| 29 ##============================================================================= | |
| 30 #######DESCRIPTIONBEGIN#### | |
| 31 ## | |
| 32 ## Author(s): nickg | |
| 33 ## Contributors: nickg | |
| 34 ## Date: 1998-02-04 | |
| 35 ## Purpose: MIPS exception vectors | |
| 36 ## Description: This file defines the code placed into the exception | |
| 37 ## vectors. It also contains the first level default VSRs | |
| 38 ## that save and restore state for both exceptions and | |
| 39 ## interrupts. | |
| 40 ## | |
| 41 ######DESCRIPTIONEND#### | |
| 42 ## | |
| 43 ##============================================================================= | |
| 44 | |
| 45 #include <pkgconf/system.h> | |
| 46 #include <pkgconf/hal.h> | |
| 47 | |
| 48 #ifdef CYGPKG_KERNEL | |
| 49 # include <pkgconf/kernel.h> | |
| 50 #endif | |
| 51 | |
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52 #include <cyg/hal/arch.inc> |
| 0 | 53 |
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54 .extern cyg_instrument |
| 2 | 55 |
| 0 | 56 ##----------------------------------------------------------------------------- |
| 57 ## Hardware supplied vectors | |
| 58 | |
| 59 .set noreorder | |
| 60 | |
| 61 .section ".reset_vector","ax" | |
| 62 | |
| 63 # Reset vector at 0xBFC00000 | |
| 64 | |
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65 FUNC_START(reset_vector) |
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66 |
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67 #ifndef CYG_HAL_STARTUP_RAM |
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68 # Decide whether this is an NMI, cold or warm boot. |
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69 |
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70 mfc0 k0,status # get status reg |
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71 lui k1,0x0008 # isolate NMI bit |
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72 and k1,k1,k0 |
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73 beqz k1,1f # skip if zero |
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74 nop |
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75 |
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76 lar k1,__nmi_entry # jump to ROM nmi code |
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77 jalr k1 |
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78 nop |
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79 1: |
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80 lui k1,0x0010 # isolate soft reset bit |
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81 and k1,k1,k0 |
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82 beqz k1,2f # skip if zero |
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83 nop |
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84 |
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85 lar k1,__warm_start # jump to ROM warm_start code |
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86 jr k1 |
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87 nop |
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88 2: |
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89 #endif |
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90 lar v0,_start # jump to start |
| 0 | 91 jr v0 |
| 92 nop # (delay slot) | |
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93 |
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94 FUNC_END(reset_vector) |
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95 |
| 0 | 96 .section ".debug_vector","ax" |
| 97 | |
| 98 # Debug vector at 0xBFC00200 | |
| 99 | |
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100 FUNC_START(debug_vector) |
| 0 | 101 la k0,32 |
| 102 la k1,hal_vsr_table # Get VSR table | |
| 103 lw k1,32*4(k1) # load debug vector | |
| 104 jr k1 # go there | |
| 105 nop # (delay slot) | |
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106 FUNC_END(debug_vector) |
| 0 | 107 |
| 108 .section ".other_vector","ax" | |
| 109 | |
| 110 # Common vector at 0x80000080 or 0xBFC00180 | |
| 111 | |
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112 FUNC_START(other_vector) |
| 0 | 113 mfc0 k0,cause # K0 = exception cause |
| 114 nop | |
| 115 andi k0,k0,0x7F # isolate exception code | |
| 116 la k1,hal_vsr_table # address of VSR table | |
| 117 add k1,k1,k0 # offset of VSR entry | |
| 118 lw k1,0(k1) # k1 = pointer to VSR | |
| 119 jr k1 # go there | |
| 120 nop # (delay slot) | |
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121 |
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122 FUNC_END(other_vector) |
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123 |
| 0 | 124 .section ".utlb_vector","ax" |
| 125 | |
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126 FUNC_START(utlb_vector) |
| 0 | 127 la k0,33 |
| 128 la k1,hal_vsr_table # Get VSR table | |
| 129 lw k1,33*4(k1) # load utlb vector | |
| 130 jr k1 # go there | |
| 131 nop # (delay slot) | |
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132 FUNC_END(utlb_vector) |
| 0 | 133 |
| 134 ##----------------------------------------------------------------------------- | |
| 135 ## Startup code | |
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136 |
| 0 | 137 .text |
| 138 | |
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139 FUNC_START(_start) |
| 0 | 140 |
| 141 # Initialize hardware | |
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142 hal_cpu_init |
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143 hal_diag_init |
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144 hal_mmu_init |
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145 hal_fpu_init |
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146 hal_memc_init |
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147 hal_intc_init |
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148 hal_cache_init |
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149 hal_timer_init |
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150 |
| 0 | 151 # Load Global Pointer register. |
| 152 la gp,_gp | |
| 153 | |
| 154 # load initial stack pointer | |
| 155 la a0,__interrupt_stack | |
| 156 move sp,a0 | |
| 157 | |
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158 hal_mon_init |
| 0 | 159 |
| 160 #ifdef CYG_HAL_STARTUP_ROM | |
| 161 # Copy data from ROM to RAM | |
| 162 | |
| 163 .extern hal_copy_data | |
| 164 jal hal_copy_data | |
| 165 nop | |
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166 |
| 0 | 167 #endif |
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168 |
| 0 | 169 # Zero BSS |
| 170 | |
| 171 .extern hal_zero_bss | |
| 172 jal hal_zero_bss | |
| 173 nop | |
| 174 | |
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175 # Call variant and platform HAL |
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176 # initialization routines. |
| 0 | 177 |
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178 .extern hal_variant_init |
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179 jal hal_variant_init |
| 2 | 180 nop |
| 181 | |
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182 .extern hal_platform_init |
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183 jal hal_platform_init |
| 2 | 184 nop |
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185 |
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186 # Call constructors |
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187 .extern cyg_hal_invoke_constructors |
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188 jal cyg_hal_invoke_constructors |
| 2 | 189 nop |
| 190 | |
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191 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) |
| 2 | 192 .extern initialize_stub |
| 193 jal initialize_stub | |
| 0 | 194 nop |
| 2 | 195 #endif |
| 0 | 196 |
| 197 # Call cyg_start | |
| 198 | |
| 199 .extern cyg_start | |
| 200 jal cyg_start | |
| 201 nop | |
| 202 | |
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203 9: b 9b # Loop if we return |
| 0 | 204 nop # (delay slot) |
| 205 | |
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206 FUNC_END(_start ) |
| 0 | 207 |
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208 |
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209 ##----------------------------------------------------------------------------- |
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210 |
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211 FUNC_START(__warm_start) |
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212 |
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213 ## The following is debug code left in here for now in case it |
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214 ## proves useful in the near future. |
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215 #if 0 |
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216 move s0,t0 |
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217 move s1,a1 |
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218 |
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219 # hal_diag_init |
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220 |
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221 hal_diag_writec '$' |
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222 mfc0 a0,$30 # get ErrorEPC |
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223 lar k0,hal_diag_ai_write_hex8 |
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224 jalr k0 |
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225 nop |
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226 hal_diag_writec '-' |
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227 move a0,s0 |
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228 jalr k0 |
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229 nop |
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230 hal_diag_writec '-' |
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231 move a0,s1 |
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232 jalr k0 |
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233 nop |
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234 1: |
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235 b 1b |
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236 nop |
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237 #endif |
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238 |
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239 # At present we treat this like an NMI. |
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240 b __nmi_entry |
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241 nop |
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242 |
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243 FUNC_END(__warm_start) |
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244 |
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245 ##----------------------------------------------------------------------------- |
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246 |
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247 FUNC_START(__nmi_entry) |
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248 |
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249 # Clear exception state |
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250 hal_cpu_except_enable |
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251 |
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252 # Move the ErrorEPC register to the EPC register so that the |
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253 # default exception handler saves the right PC value. |
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254 mfc0 k0,$30 |
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255 nop; nop; nop; |
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256 mtc0 k0,epc |
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257 nop; nop; nop; |
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258 |
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259 #if (INITIAL_SR & 0x00400000) == 0 |
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260 # Taking this exception will have set the BEV bit to 1. |
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261 # If we normally run with it zero, we must clear it here. |
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262 mfc0 k0,status |
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263 la k1,0xFFBFFFFF |
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264 and k0,k0,k1 |
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265 mtc0 k0,status |
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266 #endif |
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267 |
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268 la k0,34*4 |
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269 la k1,hal_vsr_table # Get VSR table |
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270 lw k1,34*4(k1) # load NMI vector |
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271 jr k1 # go there |
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272 nop # (delay slot) |
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273 |
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274 FUNC_END(__nmi_entry) |
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275 |
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276 |
| 0 | 277 ##----------------------------------------------------------------------------- |
| 278 ## Default exception VSR. | |
| 279 ## Saves machine state and calls external handling code. | |
| 280 | |
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281 FUNC_START(__default_exception_vsr) |
| 0 | 282 |
| 283 # We enter here with all of the CPU state still | |
| 284 # in its registers except: | |
| 285 # K0 = vector index | |
| 286 # K1 = address of this function | |
| 287 | |
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288 move k1,sp # K1 = original SP |
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289 |
| 0 | 290 #ifdef CYG_HAL_ROM_MONITOR |
| 291 # Switch to interrupt stack to handle exception | |
| 292 la sp,__interrupt_stack | |
| 293 #endif | |
| 294 | |
| 295 addi sp,sp,-mips_exception_decrement | |
| 296 # space for registers + safety margin | |
| 297 | |
| 298 sw k0,mipsreg_vector(sp) # store vector | |
| 299 | |
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300 # store GPRs |
| 0 | 301 .set noat |
| 302 sw $0,(mipsreg_regs+0*4)(sp) | |
| 303 sw $1,(mipsreg_regs+1*4)(sp) | |
| 304 sw $2,(mipsreg_regs+2*4)(sp) | |
| 305 sw $3,(mipsreg_regs+3*4)(sp) | |
| 306 sw $4,(mipsreg_regs+4*4)(sp) | |
| 307 sw $5,(mipsreg_regs+5*4)(sp) | |
| 308 sw $6,(mipsreg_regs+6*4)(sp) | |
| 309 sw $7,(mipsreg_regs+7*4)(sp) | |
| 310 sw $8,(mipsreg_regs+8*4)(sp) | |
| 311 sw $9,(mipsreg_regs+9*4)(sp) | |
| 312 sw $10,(mipsreg_regs+10*4)(sp) | |
| 313 sw $11,(mipsreg_regs+11*4)(sp) | |
| 314 sw $12,(mipsreg_regs+12*4)(sp) | |
| 315 sw $13,(mipsreg_regs+13*4)(sp) | |
| 316 sw $14,(mipsreg_regs+14*4)(sp) | |
| 317 sw $15,(mipsreg_regs+15*4)(sp) | |
| 318 sw $16,(mipsreg_regs+16*4)(sp) | |
| 319 sw $17,(mipsreg_regs+17*4)(sp) | |
| 320 sw $18,(mipsreg_regs+18*4)(sp) | |
| 321 sw $19,(mipsreg_regs+19*4)(sp) | |
| 322 sw $20,(mipsreg_regs+20*4)(sp) | |
| 323 sw $21,(mipsreg_regs+21*4)(sp) | |
| 324 sw $22,(mipsreg_regs+22*4)(sp) | |
| 325 sw $23,(mipsreg_regs+23*4)(sp) | |
| 326 sw $24,(mipsreg_regs+24*4)(sp) | |
| 327 sw $25,(mipsreg_regs+25*4)(sp) | |
| 328 # sw $26,(mipsreg_regs+26*4)(sp) # == K0 | |
| 329 # sw $27,(mipsreg_regs+27*4)(sp) # == K1 | |
| 330 sw $28,(mipsreg_regs+28*4)(sp) # == GP | |
| 331 # sw $29,(mipsreg_regs+29*4)(sp) # == SP | |
| 332 sw $30,(mipsreg_regs+30*4)(sp) # == FP | |
| 333 sw $31,(mipsreg_regs+31*4)(sp) # == RA | |
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334 .set at |
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335 |
| 0 | 336 mfhi a0 |
| 337 mflo a1 | |
| 338 sw a0,mipsreg_hi(sp) | |
| 339 sw a1,mipsreg_lo(sp) | |
| 340 | |
| 341 # K1 contains original SP | |
| 342 sw k1,(mipsreg_regs+29*4)(sp) # store in reg dump | |
| 343 | |
| 344 # save remaining machine state registers | |
| 345 mfc0 t0,cause | |
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346 mfc0 t1,status |
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347 mfc0 t2,cache |
| 0 | 348 mfc0 t3,badvr |
| 349 mfc0 t4,config | |
| 350 mfc0 t5,prid | |
| 351 mfc0 t6,epc | |
| 352 | |
| 353 sw t0,mipsreg_cause(sp) | |
| 354 sw t1,mipsreg_sr(sp) | |
| 355 sw t2,mipsreg_cache(sp) | |
| 356 sw t3,mipsreg_badvr(sp) | |
| 357 sw t4,mipsreg_config(sp) | |
| 358 sw t5,mipsreg_prid(sp) | |
| 359 sw t6,mipsreg_pc(sp) | |
| 360 | |
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361 hal_fpu_save sp |
| 0 | 362 |
| 363 # The machine state is now all saved on the stack. | |
| 364 | |
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365 hal_diag_excpt_start |
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366 |
| 0 | 367 # Load Global Pointer register. |
| 368 la gp,_gp | |
| 369 | |
| 370 move s0,sp # save pointer to saved state | |
| 371 | |
| 372 addi sp,sp,-mips_stack_frame_size # make a null frame | |
| 373 | |
| 374 # Need to set up back pointers etc. ??? | |
| 375 | |
| 376 la ra,restore_state # load return address | |
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377 |
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378 hal_cpu_except_enable # reenable exceptions |
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379 |
| 0 | 380 .extern exception_handler |
| 381 j exception_handler # call C code | |
| 382 move a0,s0 # arg0 = register dump (delay slot) | |
| 383 | |
| 384 # When the exception handler returns, it will | |
| 385 # go back to restore_state, below. | |
| 386 | |
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387 FUNC_END(__default_exception_vsr) |
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388 |
| 0 | 389 ##------------------------------------------------------------------------------ |
| 390 ## Default interrupt VSR. | |
| 391 ## Saves machine state and calls appropriate ISR. When done, calls | |
| 392 ## interrupt_end() to finish up and possibly reschedule. | |
| 393 | |
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394 FUNC_START(__default_interrupt_vsr) |
| 0 | 395 |
| 396 | |
| 397 # We enter here with all of the CPU state still | |
| 398 # in its registers except: | |
| 399 # K0 = vector index | |
| 400 # K1 = address of this function | |
| 401 | |
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402 move k1,sp # K1 = original SP |
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403 |
| 0 | 404 addi sp,sp,-mips_exception_decrement |
| 405 # space for registers + safety margin | |
| 406 | |
| 407 sw k0,mipsreg_vector(sp) # store vector | |
| 408 | |
| 409 # store GPRs | |
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410 .set noat |
| 0 | 411 sw $0,(mipsreg_regs+0*4)(sp) |
| 412 sw $1,(mipsreg_regs+1*4)(sp) | |
| 413 sw $2,(mipsreg_regs+2*4)(sp) | |
| 414 sw $3,(mipsreg_regs+3*4)(sp) | |
| 415 sw $4,(mipsreg_regs+4*4)(sp) | |
| 416 sw $5,(mipsreg_regs+5*4)(sp) | |
| 417 sw $6,(mipsreg_regs+6*4)(sp) | |
| 418 sw $7,(mipsreg_regs+7*4)(sp) | |
| 419 sw $8,(mipsreg_regs+8*4)(sp) | |
| 420 sw $9,(mipsreg_regs+9*4)(sp) | |
| 421 sw $10,(mipsreg_regs+10*4)(sp) | |
| 422 sw $11,(mipsreg_regs+11*4)(sp) | |
| 423 sw $12,(mipsreg_regs+12*4)(sp) | |
| 424 sw $13,(mipsreg_regs+13*4)(sp) | |
| 425 sw $14,(mipsreg_regs+14*4)(sp) | |
| 426 sw $15,(mipsreg_regs+15*4)(sp) | |
| 427 sw $16,(mipsreg_regs+16*4)(sp) | |
| 428 sw $17,(mipsreg_regs+17*4)(sp) | |
| 429 sw $18,(mipsreg_regs+18*4)(sp) | |
| 430 sw $19,(mipsreg_regs+19*4)(sp) | |
| 431 sw $20,(mipsreg_regs+20*4)(sp) | |
| 432 sw $21,(mipsreg_regs+21*4)(sp) | |
| 433 sw $22,(mipsreg_regs+22*4)(sp) | |
| 434 sw $23,(mipsreg_regs+23*4)(sp) | |
| 435 sw $24,(mipsreg_regs+24*4)(sp) | |
| 436 sw $25,(mipsreg_regs+25*4)(sp) | |
| 437 # sw $26,(mipsreg_regs+26*4)(sp) # == K0 | |
| 438 # sw $27,(mipsreg_regs+27*4)(sp) # == K1 | |
| 439 sw $28,(mipsreg_regs+28*4)(sp) # == GP | |
| 440 # sw $29,(mipsreg_regs+29*4)(sp) # == SP | |
| 441 sw $30,(mipsreg_regs+30*4)(sp) # == FP | |
| 442 sw $31,(mipsreg_regs+31*4)(sp) # == RA | |
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443 .set at |
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444 |
| 0 | 445 mfhi a0 |
| 446 mflo a1 | |
| 447 sw a0,mipsreg_hi(sp) | |
| 448 sw a1,mipsreg_lo(sp) | |
| 449 | |
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450 # K1 contains original SP |
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451 sw k1,(mipsreg_regs+29*4)(sp) # store in reg dump |
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452 |
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453 mfc0 t1,status |
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454 mfc0 t2,cache |
| 0 | 455 mfc0 t3,epc |
| 456 | |
| 457 sw t1,mipsreg_sr(sp) | |
| 458 sw t2,mipsreg_cache(sp) | |
| 459 sw t3,mipsreg_pc(sp) | |
| 460 | |
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461 hal_fpu_save sp |
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462 |
| 0 | 463 # The machine state is now all saved on the stack. |
| 464 | |
| 465 # Load Global Pointer register. | |
| 466 la gp,_gp | |
| 467 | |
| 468 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 2 | 469 .extern cyg_scheduler_sched_lock |
| 470 la v0,cyg_scheduler_sched_lock | |
| 0 | 471 lw a0,0(v0) |
| 472 addi a0,a0,1 | |
| 473 sw a0,0(v0) | |
| 474 #endif | |
| 475 | |
| 476 move s0,sp # save pointer to saved state | |
| 477 | |
| 478 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 479 | |
| 480 la a0,__interrupt_stack # a0 = stack top | |
| 481 la a1,__interrupt_stack_base # a1 = stack base | |
| 482 sub a3,sp,a1 # a3 = sp - base | |
| 483 bltz a3,1f # if < 0 - not on istack | |
| 484 nop # delay slot | |
| 485 sub t0,a0,sp # t0 = top - sp | |
| 486 bgtz t0,8f # if > 0 - already on istack | |
| 487 nop # delay slot | |
| 488 1: | |
| 489 move sp,a0 # switch to istack | |
| 490 8: | |
| 491 addi sp,sp,-4 # space for old SP | |
| 492 sw s0,0(sp) # save old SP on stack | |
| 493 | |
| 494 #endif | |
| 495 | |
| 496 subu sp,sp,mips_stack_frame_size # make a null frame | |
| 497 | |
| 498 # Need to set up back pointers etc. ??? | |
| 499 | |
| 500 # Decode external interrupt via interrupt controller | |
| 501 | |
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502 hal_intc_decode s2 |
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503 |
| 0 | 504 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN |
| 505 move s1,zero # Just vector zero is supported | |
| 506 #else | |
| 507 move s1,s2 # Vector == interrupt number | |
| 508 #endif | |
| 509 | |
| 510 # Here s1 is the number of the vector to be called and s2 is | |
| 511 # the number of the interrupt being serviced. | |
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512 |
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513 hal_diag_intr_start |
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514 |
| 0 | 515 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) |
| 516 | |
| 517 # Call cyg_instrument to record that this interrupt is being raised. | |
| 518 | |
| 519 li a0,0x0301 # a0 = type = INTR,RAISE | |
| 520 move a1,s1 # a1 = vector number | |
| 521 jal cyg_instrument # call instrument function | |
| 522 xor a2,a2,a2 # arg2 = 0 (delay slot) | |
| 523 #endif | |
| 524 | |
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525 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) |
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526 # If we are supporting Ctrl-C interrupts from GDB, we must squirrel |
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527 # away a pointer to the save interrupt state here so that we can |
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528 # plant a breakpoint at some later time. |
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529 |
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530 .extern hal_saved_interrupt_state |
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531 la v0,hal_saved_interrupt_state |
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532 sw s0,0(v0) |
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533 |
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534 #endif |
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535 |
| 0 | 536 sll s1,s1,2 # s1 = byte offset of vector |
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537 |
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538 hal_cpu_except_enable # reenable exceptions |
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539 |
| 0 | 540 la t2,hal_interrupt_handlers # handler table |
| 541 add t2,t2,s1 # address of ISR ptr | |
| 542 lw t2,0(t2) # ISR pointer | |
| 543 | |
| 544 la a1,hal_interrupt_data # data table | |
| 545 add a1,a1,s1 # address of data ptr | |
| 546 lw a1,0(a1) # Data pointer | |
| 547 | |
| 548 move a0,s2 # pass interrupt number | |
| 2 | 549 |
| 0 | 550 jalr t2 # call ISR via t2 |
| 551 nop # (delay slot) | |
| 552 | |
| 553 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 554 | |
| 555 # If we are returning from the last nested interrupt, move back | |
| 556 # to the thread stack. interrupt_end() must be called on the | |
| 557 # thread stack since it potentially causes a context switch. | |
| 558 # Since we have arranged for the top of stack location to | |
| 559 # contain the sp we need to go back to here, just pop it off | |
| 560 # and put it in SP. | |
| 561 | |
| 562 | |
| 563 lw sp,mips_stack_frame_size(sp) # sp = *sp | |
| 564 subu sp,sp,mips_stack_frame_size # make a null frame | |
| 565 #endif | |
| 566 | |
| 567 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 568 | |
| 569 # We only need to call _interrupt_end() when there is a kernel | |
| 570 # present to do any tidying up. | |
| 571 | |
| 572 # On return v0 bit 1 will indicate whether a DSR is | |
| 573 # to be posted. Pass this together with a pointer to | |
| 574 # the interrupt object we have just used to the | |
| 575 # interrupt tidy up routine. | |
| 576 | |
| 577 # Note that s0, s1 and s2 are defined to be preserved across | |
| 578 # calls by the calling convention, so they still contain | |
| 579 # the register dump, the vector offset and the interrupt number | |
| 580 # respectively. | |
| 581 | |
| 582 move a0,v0 # put ISR result in arg0 | |
| 583 | |
| 584 la a1,hal_interrupt_objects # interrupt object table | |
| 585 add a1,a1,s1 # address of object ptr | |
| 586 lw a1,0(a1) # a1 = object ptr | |
| 587 | |
| 588 move a2,s0 # arg3 = saved register dump | |
| 589 | |
| 590 .extern interrupt_end | |
| 591 jal interrupt_end # call into C to finish off | |
| 592 nop # (delay slot) | |
| 593 | |
| 594 #endif | |
| 595 | |
| 596 restore_state: | |
| 597 | |
| 598 # All done, restore CPU state and continue | |
| 599 | |
| 600 addi sp,sp,mips_stack_frame_size # retrieve CPU state ptr | |
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601 |
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602 # Disable interrupts again while we restore state. |
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603 |
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604 hal_diag_restore |
| 0 | 605 |
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606 hal_fpu_load sp |
| 0 | 607 |
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608 lw t0,mipsreg_cache(sp) |
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609 lw t1,mipsreg_hi(sp) |
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610 lw t2,mipsreg_lo(sp) |
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611 |
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612 mtc0 t0,cache |
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613 mthi t1 |
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614 mtlo t2 |
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615 |
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616 # load GPRs |
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617 .set noat |
| 0 | 618 # lw $0,(mipsreg_regs+0*4)(sp) |
| 619 lw $1,(mipsreg_regs+1*4)(sp) | |
| 620 lw $2,(mipsreg_regs+2*4)(sp) | |
| 621 lw $3,(mipsreg_regs+3*4)(sp) | |
| 622 lw $4,(mipsreg_regs+4*4)(sp) | |
| 623 lw $5,(mipsreg_regs+5*4)(sp) | |
| 624 lw $6,(mipsreg_regs+6*4)(sp) | |
| 625 lw $7,(mipsreg_regs+7*4)(sp) | |
| 626 lw $8,(mipsreg_regs+8*4)(sp) | |
| 627 lw $9,(mipsreg_regs+9*4)(sp) | |
| 628 lw $10,(mipsreg_regs+10*4)(sp) | |
| 629 lw $11,(mipsreg_regs+11*4)(sp) | |
| 630 lw $12,(mipsreg_regs+12*4)(sp) | |
| 631 lw $13,(mipsreg_regs+13*4)(sp) | |
| 632 lw $14,(mipsreg_regs+14*4)(sp) | |
| 633 lw $15,(mipsreg_regs+15*4)(sp) | |
| 634 lw $16,(mipsreg_regs+16*4)(sp) | |
| 635 lw $17,(mipsreg_regs+17*4)(sp) | |
| 636 lw $18,(mipsreg_regs+18*4)(sp) | |
| 637 lw $19,(mipsreg_regs+19*4)(sp) | |
| 638 lw $20,(mipsreg_regs+20*4)(sp) | |
| 639 lw $21,(mipsreg_regs+21*4)(sp) | |
| 640 lw $22,(mipsreg_regs+22*4)(sp) | |
| 641 lw $23,(mipsreg_regs+23*4)(sp) | |
| 642 lw $24,(mipsreg_regs+24*4)(sp) | |
| 643 lw $25,(mipsreg_regs+25*4)(sp) | |
| 644 # lw $26,(mipsreg_regs+26*4)(sp) # == K0 | |
| 645 # lw $27,(mipsreg_regs+27*4)(sp) # == K1 | |
| 646 lw $28,(mipsreg_regs+28*4)(sp) # == GP | |
| 647 # lw $29,(mipsreg_regs+29*4)(sp) # == SP | |
| 648 lw $30,(mipsreg_regs+30*4)(sp) # == FP | |
| 649 lw $31,(mipsreg_regs+31*4)(sp) # == RA | |
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650 .set at |
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651 |
| 0 | 652 lw k0,mipsreg_pc(sp) # K0 = return PC |
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653 lw k1,mipsreg_sr(sp) # K1 = saved SR |
| 0 | 654 lw sp,(mipsreg_regs+29*4)(sp) # load SP |
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655 |
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656 # Invoke CPU specific mechanism for returning from this |
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657 # exception |
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658 |
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659 hal_cpu_eret k0,k1 |
| 0 | 660 |
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661 FUNC_END(__default_interrupt_vsr) |
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662 |
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663 hal_intc_decode_data |
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664 |
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665 ##----------------------------------------------------------------------------- |
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666 ## Execute pending DSRs on the interrupt stack with interrupts enabled. |
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667 ## Note: this can only be called from code running on a thread stack |
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668 |
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669 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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670 .extern cyg_interrupt_call_pending_DSRs |
| 0 | 671 |
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672 FUNC_START(hal_interrupt_stack_call_pending_DSRs) |
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673 mfc0 t0,status # get status register value |
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674 la v0,__interrupt_stack # v0 = interrupt stack |
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675 move v1,sp # v1 = original stack ptr |
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676 move sp,v0 # sp = interrupt stack |
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677 addi sp,sp,-32 # make a null frame |
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678 sw v1,16(sp) # save old sp |
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679 sw ra,20(sp) # save old ra |
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680 sw t0,24(sp) # save old sr |
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681 |
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682 hal_cpu_int_enable |
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683 |
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684 jal cyg_interrupt_call_pending_DSRs # call back to kernel |
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685 nop |
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686 |
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687 lw a0,24(sp) # get status reg |
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688 |
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689 hal_cpu_int_merge a0 # merge with current SR |
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690 |
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691 lw ra,20(sp) # restore ra |
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692 lw sp,16(sp) # restore sp |
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693 |
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694 jr ra # go back |
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695 nop # delay slot |
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696 |
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697 FUNC_END(hal_interrupt_stack_call_pending_DSRs) |
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698 #endif |
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699 |
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700 ##----------------------------------------------------------------------------- |
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701 ## Short circuit in case any code tries to use "__gccmain()" |
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702 |
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703 FUNC_START(__gccmain) |
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704 jr ra |
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705 nop |
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706 FUNC_END(__gccmain) |
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707 |
| 0 | 708 ##----------------------------------------------------------------------------- |
| 709 ## Interrupt Stack. | |
| 710 ## Used during intialization and for executing ISRs. | |
| 711 | |
| 712 .bss | |
| 713 | |
| 714 .balign 16 | |
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715 .global cyg_interrupt_stack_base |
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716 cyg_interrupt_stack_base: |
| 0 | 717 __interrupt_stack_base: |
| 718 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 719 .byte 0 | |
| 720 .endr | |
| 721 .balign 16 | |
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722 .global cyg_interrupt_stack |
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723 cyg_interrupt_stack: |
| 0 | 724 __interrupt_stack: |
| 725 | |
| 726 .long 0,0,0,0,0,0,0,0 | |
| 727 | |
| 728 ##----------------------------------------------------------------------------- | |
| 729 ## VSR table. | |
| 730 ## The main interrupt code indirects through here to find the VSR | |
| 731 ## to execute for each architecture defined interrupt. | |
| 732 ## This is only used for simulated targets, on real targets a fixed location VSR | |
| 733 ## table is now allocated at 0x80000100. | |
| 734 | |
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735 #ifndef CYG_HAL_MIPS_VSR_TABLE_DEFINED |
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736 |
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737 ## .section ".vsr_table","a" |
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738 |
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739 .data |
| 0 | 740 |
| 741 .globl hal_vsr_table | |
| 742 | |
| 743 hal_vsr_table: | |
| 744 .long __default_interrupt_vsr | |
| 745 .rept 63 | |
| 746 .long __default_exception_vsr | |
| 747 .endr | |
| 748 | |
| 749 #endif | |
| 750 | |
| 751 #------------------------------------------------------------------------------ | |
| 752 # Interrupt vector tables. | |
| 753 # These tables contain the isr, data and object pointers used to deliver | |
| 754 # interrupts to user code. | |
| 755 # hal_interrupt_level contains the interrupt level set by | |
| 756 # HAL_INTERRUPT_CONFIGURE(). | |
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757 # This is a default set that provide support only for the 6 external |
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758 # interrupts in the status/cause registers. Platforms or boards are expected |
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759 # to define their own versions of these if they have their own interrupt mappings. |
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760 |
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761 #ifndef CYG_HAL_MIPS_ISR_TABLES_DEFINED |
| 0 | 762 |
| 763 .extern hal_default_isr | |
| 764 | |
| 765 .data | |
| 766 | |
| 767 .globl hal_interrupt_handlers | |
| 768 hal_interrupt_handlers: | |
| 769 .long hal_default_isr | |
| 770 .long hal_default_isr | |
| 771 .long hal_default_isr | |
| 772 .long hal_default_isr | |
| 773 .long hal_default_isr | |
| 774 .long hal_default_isr | |
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775 |
| 0 | 776 |
| 777 .globl hal_interrupt_data | |
| 778 hal_interrupt_data: | |
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779 .rept 6 |
| 0 | 780 .long 0 |
| 781 .endr | |
| 782 | |
| 783 .globl hal_interrupt_objects | |
| 784 hal_interrupt_objects: | |
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785 .rept 6 |
| 0 | 786 .long 0 |
| 787 .endr | |
| 788 | |
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789 #endif |
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790 |
| 0 | 791 ##----------------------------------------------------------------------------- |
| 792 ## end of vectors.S | |
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793 |
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794 |
