Mercurial > ecos
annotate packages/hal/arm/arch/current/src/vectors.S @ 58:6e51d764f8f1 ecos-sw-1999-12-10
Merge from eCos master repository on 1999-12-10-07:47:04-GMT
| author | jlarmour |
|---|---|
| date | Fri, 10 Dec 1999 15:30:44 +0000 |
| parents | 755351606154 |
| children | c38311975d4f |
| rev | line source |
|---|---|
| 2 | 1 // #======================================================================== |
| 2 // # | |
| 3 // # vectors.S | |
| 4 // # | |
| 5 // # ARM exception vectors | |
| 6 // # | |
| 7 // #======================================================================== | |
| 8 // ####COPYRIGHTBEGIN#### | |
| 9 // | |
| 10 // ------------------------------------------- | |
| 11 // The contents of this file are subject to the Cygnus eCos Public License | |
| 12 // Version 1.0 (the "License"); you may not use this file except in | |
| 13 // compliance with the License. You may obtain a copy of the License at | |
| 14 // http://sourceware.cygnus.com/ecos | |
| 15 // | |
| 16 // Software distributed under the License is distributed on an "AS IS" | |
| 17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 18 // License for the specific language governing rights and limitations under | |
| 19 // the License. | |
| 20 // | |
| 21 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 22 // September 30, 1998. | |
| 23 // | |
| 24 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 25 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. | |
| 26 // ------------------------------------------- | |
| 27 // | |
| 28 // ####COPYRIGHTEND#### | |
| 29 // #======================================================================== | |
| 30 // ######DESCRIPTIONBEGIN#### | |
| 31 // # | |
| 32 // # Author(s): nickg, gthomas | |
| 33 // # Contributors: nickg, gthomas | |
| 34 // # Date: 1999-02-20 | |
| 35 // # Purpose: ARM exception vectors | |
| 36 // # Description: This file defines the code placed into the exception | |
| 37 // # vectors. It also contains the first level default VSRs | |
| 38 // # that save and restore state for both exceptions and | |
| 39 // # interrupts. | |
| 40 // # | |
| 41 // #####DESCRIPTIONEND#### | |
| 42 // # | |
| 43 // #======================================================================== | |
| 44 | |
| 45 #include <pkgconf/hal.h> | |
| 46 #include <pkgconf/hal_arm.h> | |
| 47 #ifdef CYGPKG_KERNEL // no CDL yet | |
| 48 #include <pkgconf/kernel.h> | |
| 49 #else | |
| 50 # undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
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51 # undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
| 2 | 52 #endif |
| 53 #include <cyg/hal/hal_platform_setup.h> | |
| 54 | |
| 55 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 56 // The CDL should enforce this | |
| 57 #undef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 58 #endif | |
| 59 | |
| 60 #include "arm.inc" | |
| 61 | |
| 62 #define FUNC_START(name) \ | |
| 63 .globl _name; \ | |
| 64 _name: | |
| 65 | |
| 66 #define PTR(name) \ | |
| 67 .##name: .word name | |
| 68 | |
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69 #ifdef CYGHWR_HAL_ARM_HAS_MMU |
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70 #define UNMAPPED(x) ((x)-__exception_handlers) |
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71 #else |
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72 #define UNMAPPED(x) (x) |
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73 #endif |
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74 |
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75 #define UNMAPPED_PTR(name) \ |
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76 .##name: .word UNMAPPED(name) |
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77 |
| 2 | 78 |
| 79 .file "vectors.S" | |
| 80 | |
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81 |
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82 // CYGHWR_LED_MACRO can be defined in hal_platform_setup.h. It's free to |
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83 // use r0+r1. Argument is in "\x" - cannot use macro arguments since the |
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84 // macro may contain #-chars and use of arguments cause these to be |
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85 // interpreted as CPP stringify operators. |
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86 // See example in PID hal_platform_setup.h. |
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87 #ifndef CYGHWR_LED_MACRO |
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88 #define CYGHWR_LED_MACRO |
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89 #endif |
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90 |
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91 .macro LED x |
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92 CYGHWR_LED_MACRO |
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93 .endm |
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94 |
| 2 | 95 |
| 96 //========================================================================== | |
| 97 // Hardware exception vectors. | |
| 98 // This entire section will be copied to location 0x0000 at startup time. | |
| 99 // | |
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100 .code 32 |
| 2 | 101 .section ".vectors","ax" |
| 102 .global __exception_handlers | |
| 103 __exception_handlers: | |
| 104 ldr pc,.reset_vector // 0x00 | |
| 105 ldr pc,.undefined_instruction // 0x04 | |
| 106 ldr pc,.software_interrupt // 0x08 start && software int | |
| 107 ldr pc,.abort_prefetch // 0x0C | |
| 108 ldr pc,.abort_data // 0x10 | |
| 109 .word 0 // unused | |
| 110 ldr pc,.IRQ // 0x18 | |
| 111 ldr pc,.FIQ // 0x1C | |
| 112 | |
| 113 // The layout of these pointers should match the vector table above since | |
| 114 // they are copied in pairs. | |
| 115 .global vectors | |
| 116 vectors: | |
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117 UNMAPPED_PTR(reset_vector) // 0x20 |
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118 PTR(undefined_instruction) // 0x24 |
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119 PTR(software_interrupt) // 0x28 |
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120 PTR(abort_prefetch) // 0x2C |
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121 PTR(abort_data) // 0x30 |
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122 .word 0 // 0x34 |
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123 PTR(IRQ) // 0x38 |
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124 PTR(FIQ) // 0x3c |
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125 PTR(start) // This is copied to 0x28 for bootup // 0x40 |
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126 // location 0x40 is used for storing DRAM size if known |
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127 // for some platforms. |
| 2 | 128 |
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129 // Other vectors |
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130 .balign 16 // Should be at 0x50 |
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131 .balign 32 |
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132 |
| 2 | 133 .text |
| 134 // Startup code which will get the machine into supervisor mode | |
| 135 .global reset_vector | |
| 136 .type reset_vector,function | |
| 137 reset_vector: | |
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138 PLATFORM_SETUP1 // Early stage platform initialization |
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139 // which can set DRAM size at 0x40 |
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140 // see <cyg/hal/hal_platform_setup.h> |
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141 |
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142 // Come here to reset board |
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143 warm_reset: |
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144 |
| 2 | 145 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 146 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 147 mrs r7,cpsr // move back to IRQ mode | |
| 148 and r7,r7,#CPSR_MODE_BITS | |
| 149 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 150 beq start | |
| 151 #endif | |
| 152 | |
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153 // We cannot access any LED registers until after PLATFORM_SETUP1 |
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154 LED 7 |
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155 |
| 2 | 156 mov r0,#0 // move vectors |
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157 // We cannot perform a store until after PLATFORM_SETUP1 |
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158 str r0, [r0,#0x40] // DRAM size to zero => unknown |
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159 |
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160 ldr r1,=__exception_handlers |
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161 #ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
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162 // Wait with this if stubs are included (see further down). |
| 2 | 163 ldr r2,[r1,#0x04] // undefined instruction |
| 164 str r2,[r0,#0x04] | |
| 165 ldr r2,[r1,#0x24] | |
| 166 str r2,[r0,#0x24] | |
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167 #endif |
| 2 | 168 ldr r2,[r1,#0x08] // software interrupt |
| 169 str r2,[r0,#0x08] | |
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170 |
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171 |
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172 #if defined(CYG_HAL_STARTUP_RAM) |
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173 // Ugly hack to get into supervisor mode |
| 2 | 174 ldr r2,[r1,#0x40] |
| 175 str r2,[r0,#0x28] | |
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176 |
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177 LED 6 |
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178 |
| 2 | 179 swi // switch to supervisor mode |
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180 #endif |
| 2 | 181 |
| 182 // ========================================================================= | |
| 183 // Real startup code. We jump here from the reset vector to set up the world. | |
| 184 .globl start | |
| 185 start: | |
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186 |
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187 LED 5 |
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188 |
| 2 | 189 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 190 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 191 // If we get restarted, hang here to avoid corrupting memory | |
| 192 ldr r0,.init_flag | |
| 193 ldr r1,[r0] | |
| 194 1: cmp r1,#0 | |
| 195 bne 1b | |
| 196 ldr r1,init_done | |
| 197 str r1,[r0] | |
| 198 #endif | |
| 199 | |
| 200 // Reset software interrupt pointer | |
| 201 mov r0,#0 // move vectors | |
| 202 ldr r1,.__exception_handlers | |
| 203 #if defined(CYG_HAL_STARTUP_RAM) && \ | |
| 204 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 205 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 206 beq 10f | |
| 207 #endif | |
| 208 ldr r2,[r1,#0x28] // software interrupt | |
| 209 str r2,[r0,#0x28] | |
| 210 10: | |
| 211 ldr r2,[r1,#0x18] // IRQ | |
| 212 str r2,[r0,#0x18] | |
| 213 ldr r2,[r1,#0x38] | |
| 214 str r2,[r0,#0x38] | |
| 215 ldr r2,[r1,#0x1C] // FIQ | |
| 216 str r2,[r0,#0x1C] | |
| 217 ldr r2,[r1,#0x3C] | |
| 218 str r2,[r0,#0x3C] | |
| 219 ldr r2,[r1,#0x0C] // abort (prefetch) | |
| 220 str r2,[r0,#0x0C] | |
| 221 ldr r2,[r1,#0x2C] | |
| 222 str r2,[r0,#0x2C] | |
| 223 ldr r2,[r1,#0x10] // abort (data) | |
| 224 str r2,[r0,#0x10] | |
| 225 ldr r2,[r1,#0x30] | |
| 226 str r2,[r0,#0x30] | |
| 227 | |
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228 LED 4 |
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229 |
| 2 | 230 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) |
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231 // Set up reset vector |
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232 ldr r2,[r1,#0x00] // reset vector intstruction |
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233 str r2,[r0,#0x00] |
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234 ldr r2,=warm_reset |
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235 str r2,[r0,#0x20] |
| 2 | 236 // Relocate [copy] data from ROM to RAM |
| 237 ldr r3,.__rom_data_start | |
| 238 ldr r4,.__ram_data_start | |
| 239 ldr r5,.__ram_data_end | |
| 240 cmp r4,r5 // jump if no data to move | |
| 241 beq 2f | |
| 242 sub r3,r3,#4 // loop adjustments | |
| 243 sub r4,r4,#4 | |
| 244 1: ldr r0,[r3,#4]! // copy info | |
| 245 str r0,[r4,#4]! | |
| 246 cmp r4,r5 | |
| 247 bne 1b | |
| 248 2: | |
| 249 #endif | |
| 250 | |
| 251 // initialize interrupt/exception environments | |
| 252 ldr sp,.__startup_stack | |
| 253 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE) | |
| 254 msr cpsr,r0 | |
| 255 ldr sp,.__exception_stack | |
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256 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_FIQ_MODE) |
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257 msr cpsr,r0 |
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258 ldr sp,.__FIQ_exception_stack |
| 2 | 259 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE) |
| 260 msr cpsr,r0 | |
| 261 ldr sp,.__exception_stack | |
| 262 | |
| 263 // initialize CPSR (machine state register) | |
| 264 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) | |
| 265 msr cpsr,r0 | |
| 266 | |
| 267 // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!! | |
| 268 msr spsr,r0 | |
| 269 | |
| 270 // initialize stack | |
| 271 ldr sp,.__startup_stack | |
| 272 | |
| 273 // clear BSS | |
| 274 ldr r1,.__bss_start | |
| 275 ldr r2,.__bss_end | |
| 276 mov r0,#0 | |
| 277 cmp r1,r2 | |
| 278 beq 2f | |
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279 1: str r0,[r1],#4 |
| 2 | 280 cmp r1,r2 |
| 281 bne 1b | |
| 282 2: | |
| 283 | |
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284 |
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285 LED 3 |
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286 |
| 2 | 287 // Call platform specific hardware initialization |
| 288 bl hal_hardware_init | |
| 289 | |
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290 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
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291 bl initialize_stub |
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292 |
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293 // Now that stub is initialized, change vector. It is possible |
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294 // to single-step through most of the init code, except the below. |
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295 // Put a breakpoint at the call to cyg_hal_invoke_constructors to |
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296 // pass over this bit (s-s depends on internal state in the stub). |
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297 #endif |
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298 |
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299 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) || \ |
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300 defined(CYGIMP_HAL_PROCESS_ALL_EXCEPTIONS) |
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301 mov r0,#0 // move vectors |
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302 ldr r1,=__exception_handlers |
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303 ldr r2,[r1,#0x04] // undefined instruction |
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304 str r2,[r0,#0x04] |
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305 ldr r2,[r1,#0x24] |
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306 str r2,[r0,#0x24] |
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307 #endif |
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308 |
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309 LED 2 |
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310 |
| 2 | 311 // Run through static constructors |
| 312 bl cyg_hal_invoke_constructors | |
| 313 | |
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314 LED 1 |
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315 |
| 2 | 316 // This starts up the eCos kernel |
| 317 bl cyg_start | |
| 318 _start_hang: | |
| 319 b _start_hang | |
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320 .code 32 |
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321 |
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322 .global reset_platform |
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323 .type reset_platform,function |
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324 reset_platform: |
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325 #ifdef CYG_HAL_STARTUP_STUBS |
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326 // initialize CPSR (machine state register) |
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327 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) |
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328 msr cpsr,r0 |
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329 b warm_reset |
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330 #else |
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331 mov r0,#0 |
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332 mov pc,r0 // Jump to reset vector |
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333 #endif |
| 2 | 334 |
| 335 init_done: | |
| 336 .long 0xDEADB00B | |
| 337 | |
| 338 // | |
| 339 // Exception handlers | |
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340 // Assumption: get here from a Supervisor context [mode] |
| 2 | 341 // |
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342 .code 32 |
| 2 | 343 undefined_instruction: |
| 344 ldr sp,.__undef_exception_stack // get good stack | |
| 345 stmfd sp!,{r0,fp,ip,lr} | |
| 346 mrs r0,spsr | |
| 347 stmfd sp!,{r0} | |
| 348 mov ip,sp // save SP which will vanish with | |
| 349 // mode switch | |
| 350 mrs r0,cpsr // switch to Supervisor Mode | |
| 351 bic r0,r0,#CPSR_MODE_BITS | |
| 352 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 353 msr cpsr,r0 // sp,lr are now old values | |
| 354 mov fp,sp | |
| 355 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 356 ldr sp,.__GDB_stack | |
| 357 cmp fp,sp // already on GDB stack? | |
| 358 bhi 10f | |
| 359 ldr r0,.__GDB_stack_base | |
| 360 cmp fp,r0 | |
| 361 bls 10f // no - switch to GDB stack | |
| 362 // (already in sp) | |
| 363 mov sp,fp // yes - no switch | |
| 364 10: | |
| 365 #endif | |
| 366 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 367 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 368 ldmfd ip,{r0-r4} // saved registers | |
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369 sub r4,r4,#4 // PC at time of interrupt |
| 2 | 370 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt |
| 371 str r1,[sp,#armreg_r0] // saved R0 | |
| 372 str r2,[sp,#armreg_fp] // saved FP | |
| 373 str r3,[sp,#armreg_ip] // saved IP | |
| 374 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 375 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 376 add r0,ip,#ARMREG_SIZE | |
| 377 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 378 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 379 mov r0,sp | |
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380 bl cyg_hal_report_undefined_instruction |
| 2 | 381 #endif |
| 382 mov v1,#CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION | |
| 383 b call_exception_handler | |
| 384 | |
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385 .code 32 |
| 2 | 386 software_interrupt: |
| 387 sub sp,sp,#ARMREG_SIZE+16 // make space for frame | |
| 388 stmea sp,{r0-r10,fp} // save immediately visible registers | |
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389 mrs r0,spsr |
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390 sub r3,lr,#4 // PC at time of interrupt |
| 2 | 391 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt |
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392 str ip,[sp,#armreg_ip] // saved IP |
| 2 | 393 str r3,[sp,#armreg_pc] // PC at time of interrupt |
| 394 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
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395 add r0,sp,#ARMREG_SIZE+16 |
| 2 | 396 str r0,[sp,#armreg_sp] // SP at time of interrupt |
| 397 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 398 mov r0,sp | |
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399 bl cyg_hal_report_software_interrupt |
| 2 | 400 #endif |
| 401 mov v1,#CYGNUM_HAL_EXCEPTION_INTERRUPT | |
| 402 b call_exception_handler | |
| 403 | |
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404 .code 32 |
| 2 | 405 abort_prefetch: |
| 406 ldr sp,.__undef_exception_stack // get good stack | |
| 407 sub lr,lr,#4 // PC at time of interrupt | |
| 408 stmfd sp!,{r0,fp,ip,lr} | |
| 409 mrs r0,spsr | |
| 410 stmfd sp!,{r0} | |
| 411 mov ip,sp // save SP which will vanish with | |
| 412 // mode switch | |
| 413 mrs r0,cpsr // switch to Supervisor Mode | |
| 414 bic r0,r0,#CPSR_MODE_BITS | |
| 415 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 416 msr cpsr,r0 // sp,lr are now old values | |
| 417 mov fp,sp | |
| 418 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 419 ldr sp,.__GDB_stack | |
| 420 cmp fp,sp // already on GDB stack? | |
| 421 bhi 10f | |
| 422 ldr r0,.__GDB_stack_base | |
| 423 cmp fp,r0 | |
| 424 bls 10f // no - switch to GDB stack | |
| 425 // (already in sp) | |
| 426 mov sp,fp // yes - no switch | |
| 427 10: | |
| 428 #endif | |
| 429 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 430 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 431 ldmfd ip,{r0-r4} // saved registers | |
| 432 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 433 str r1,[sp,#armreg_r0] // saved R0 | |
| 434 str r2,[sp,#armreg_fp] // saved FP | |
| 435 str r3,[sp,#armreg_ip] // saved IP | |
| 436 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 437 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 438 add r0,ip,#ARMREG_SIZE | |
| 439 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 440 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 441 mov r0,sp | |
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442 bl cyg_hal_report_abort_prefetch |
| 2 | 443 #endif |
| 444 mov v1,#CYGNUM_HAL_EXCEPTION_CODE_ACCESS | |
| 445 b call_exception_handler | |
| 446 | |
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447 .code 32 |
| 2 | 448 abort_data: |
| 449 ldr sp,.__undef_exception_stack // get good stack | |
| 450 sub lr,lr,#4 // PC at time of interrupt | |
| 451 stmfd sp!,{r0,fp,ip,lr} | |
| 452 mrs r0,spsr | |
| 453 stmfd sp!,{r0} | |
| 454 mov ip,sp // save SP which will vanish with | |
| 455 // mode switch | |
| 456 mrs r0,cpsr // switch to Supervisor Mode | |
| 457 bic r0,r0,#CPSR_MODE_BITS | |
| 458 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 459 msr cpsr,r0 // sp,lr are now old values | |
| 460 mov fp,sp | |
| 461 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 462 ldr sp,.__GDB_stack | |
| 463 cmp fp,sp // already on GDB stack? | |
| 464 bhi 10f | |
| 465 ldr r0,.__GDB_stack_base | |
| 466 cmp fp,r0 | |
| 467 bls 10f // no - switch to GDB stack | |
| 468 // (already in sp) | |
| 469 mov sp,fp // yes - no switch | |
| 470 10: | |
| 471 #endif | |
| 472 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 473 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 474 ldmfd ip,{r0-r4} // saved registers | |
| 475 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 476 str r1,[sp,#armreg_r0] // saved R0 | |
| 477 str r2,[sp,#armreg_fp] // saved FP | |
| 478 str r3,[sp,#armreg_ip] // saved IP | |
| 479 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 480 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 481 add r0,ip,#ARMREG_SIZE | |
| 482 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 483 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 484 mov r0,sp | |
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485 bl cyg_hal_report_abort_data |
| 2 | 486 #endif |
| 487 mov v1,#CYGNUM_HAL_EXCEPTION_DATA_ACCESS | |
| 488 b call_exception_handler | |
| 489 | |
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490 |
| 2 | 491 // |
| 492 // Dispatch an exception handler. | |
| 493 | |
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494 .code 32 |
| 2 | 495 call_exception_handler: |
| 496 str v1,[sp,#armreg_vector] | |
| 497 mov r0,sp | |
| 498 bl exception_handler | |
| 499 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 500 mov r0,sp | |
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501 bl cyg_hal_report_exception_handler_returned |
| 2 | 502 #endif |
| 503 | |
| 504 // Restore [interrupted] context | |
| 505 mov ip,sp // get stack pointer | |
| 506 | |
| 507 mrs r0,cpsr // move back to IRQ mode | |
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508 orr r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
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509 msr cpsr,r0 |
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510 nop |
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511 nop |
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512 |
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513 ldr lr,[ip,#armreg_lr] |
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514 ldr sp,[sp,#armreg_sp] |
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515 |
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516 bic r0,r0,#CPSR_MODE_BITS |
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517 orr r0,r0,#CPSR_IRQ_MODE |
| 2 | 518 msr cpsr,r0 |
| 519 | |
| 520 mov sp,ip | |
| 521 ldr lr,[sp,#armreg_pc] | |
| 522 ldr r0,[sp,#armreg_cpsr] | |
| 523 ldr ip,[sp,#armreg_ip] | |
| 524 msr spsr,r0 | |
| 525 ldmfd sp,{r0-r10,fp} | |
| 526 | |
| 527 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 528 | |
| 529 // Handle device interrupts | |
| 530 // This is slightly more complicated than the other exception handlers because | |
| 531 // it needs to interface with the kernel (if present). | |
| 532 | |
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533 .code 32 |
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534 FIQ: |
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535 // Note: I use this exception stack while saving the context because |
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536 // the current SP does not seem to be always valid in this CPU mode. |
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537 ldr sp,.__FIQ_exception_stack // get good stack |
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538 sub lr,lr,#4 // PC at time of interrupt |
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539 stmfd sp!,{r0,fp,ip,lr} |
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540 mrs r0,spsr |
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541 stmfd sp!,{r0} |
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542 b handle_IRQ_or_FIQ |
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543 |
| 2 | 544 IRQ: |
| 545 // Note: I use this exception stack while saving the context because | |
| 546 // the current SP does not seem to be always valid in this CPU mode. | |
| 547 ldr sp,.__exception_stack // get good stack | |
| 548 sub lr,lr,#4 // PC at time of interrupt | |
| 549 stmfd sp!,{r0,fp,ip,lr} | |
| 550 mrs r0,spsr | |
| 551 stmfd sp!,{r0} | |
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552 |
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553 handle_IRQ_or_FIQ: |
| 2 | 554 mov ip,sp // save SP which will vanish with |
| 555 // mode switch | |
| 556 mrs r0,cpsr // switch to Supervisor Mode | |
| 557 bic r0,r0,#CPSR_MODE_BITS | |
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558 orr r0,r0,#CPSR_SUPERVISOR_MODE|CPSR_FIQ_DISABLE|CPSR_IRQ_DISABLE |
| 2 | 559 msr cpsr,r0 // sp,lr are now old values |
| 560 mov fp,sp // save old SP | |
| 561 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 562 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 563 ldmfd ip,{r0-r4} // saved registers | |
| 564 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 565 str r1,[sp,#armreg_r0] // saved R0 | |
| 566 str r2,[sp,#armreg_fp] // saved FP | |
| 567 str r3,[sp,#armreg_ip] // saved IP | |
| 568 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 569 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 570 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 571 mov v6,sp // Save pointer to register frame | |
| 572 | |
| 573 // mov r0,sp | |
| 574 // bl _show_frame_in | |
| 575 | |
| 576 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 577 // Switch to interrupt stack | |
| 578 ldr r2,.irq_level // current number of nested interrupts | |
| 579 ldr r0,[r2] | |
| 580 add r1,r0,#1 | |
| 581 str r1,[r2] // if was zero, switch stacks | |
| 582 cmp r0,#0 | |
| 583 moveq r1,sp // save old stack pointer | |
| 584 ldreq sp,.__interrupt_stack | |
| 585 stmeqfd sp!,{r1} | |
| 586 10: | |
| 587 #endif | |
| 588 | |
| 589 // The entire CPU state is now stashed on the stack, | |
| 590 // increment the scheduler lock and handle the interrupt | |
| 591 | |
| 592 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 593 .extern cyg_scheduler_sched_lock | |
| 594 ldr r3,.cyg_scheduler_sched_lock | |
| 595 ldr r4,[r3] | |
| 596 add r4,r4,#1 | |
| 597 str r4,[r3] | |
| 598 #endif | |
| 599 | |
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600 mov r0,v6 |
| 2 | 601 bl hal_IRQ_handler // determine interrupt source |
| 602 mov v1,r0 // returned vector # | |
| 603 | |
| 604 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \ | |
| 605 defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 606 ldr r0,=RAISE_INTR // arg0 = type = INTR,RAISE | |
| 607 mov r1,v1 // arg1 = vector | |
| 608 mov r2,#0 // arg2 = 0 | |
| 609 bl cyg_instrument // call instrument function | |
| 610 #endif | |
| 611 | |
| 612 mov r0,v1 // vector # | |
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613 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS |
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614 cmp r0,#0 // ignore spurious interrupts |
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615 beq spurious_IRQ |
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616 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS |
| 2 | 617 ldr r1,.hal_interrupt_data |
| 618 ldr r1,[r1,v1,lsl #2] // handler data | |
| 619 ldr r2,.hal_interrupt_handlers | |
| 620 ldr v3,[r2,v1,lsl #2] // handler (indexed by vector #) | |
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621 mov r2,v6 // register frame (this is necessary |
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622 // for the ISR too, for ^C detection) |
| 2 | 623 |
| 624 mov lr,pc // invoke handler (call indirect | |
| 625 mov pc,v3 // thru v3) | |
| 626 | |
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627 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS |
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628 spurious_IRQ: |
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629 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS |
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630 |
| 2 | 631 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
| 632 // If we are returning from the last nested interrupt, move back | |
| 633 // to the thread stack. interrupt_end() must be called on the | |
| 634 // thread stack since it potentially causes a context switch. | |
| 635 ldr r2,.irq_level | |
| 636 ldr r3,[r2] | |
| 637 subs r1,r3,#1 | |
| 638 str r1,[r2] | |
| 639 ldreq sp,[sp] // This should be the saved stack pointer | |
| 640 #endif | |
| 641 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 642 // The return value from the handler (in r0) will indicate whether a | |
| 643 // DSR is to be posted. Pass this together with a pointer to the | |
| 644 // interrupt object we have just used to the interrupt tidy up routine. | |
| 645 | |
| 646 ldr r1,.hal_interrupt_objects | |
| 647 ldr r1,[r1,v1,lsl #2] | |
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648 mov r2,v6 // register frame |
| 2 | 649 bl interrupt_end // post any bottom layer handler |
| 650 // threads and call scheduler | |
| 651 #endif | |
| 652 | |
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653 |
| 2 | 654 // mov r0,sp |
| 655 // bl show_frame_out | |
| 656 | |
| 657 mov ip,sp // get stack pointer | |
| 658 | |
| 659 mrs r0,cpsr // move back to IRQ mode | |
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660 orr r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
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661 msr cpsr,r0 |
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662 nop |
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663 nop |
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664 |
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665 ldr lr,[ip,#armreg_lr] |
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666 ldr sp,[sp,#armreg_sp] |
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667 |
| 2 | 668 bic r0,r0,#CPSR_MODE_BITS |
| 669 orr r0,r0,#CPSR_IRQ_MODE | |
| 670 msr cpsr,r0 | |
| 671 | |
| 672 mov sp,ip | |
| 673 ldr lr,[sp,#armreg_pc] | |
| 674 ldr r0,[sp,#armreg_cpsr] | |
| 675 ldr ip,[sp,#armreg_ip] | |
| 676 msr spsr,r0 | |
| 677 ldmfd sp,{r0-r10,fp} | |
| 678 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 679 | |
| 680 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 681 // Execute pending DSRs the interrupt stack | |
| 682 // Note: this can only be called from code running on a thread stack | |
| 683 .global hal_interrupt_stack_call_pending_DSRs | |
| 684 hal_interrupt_stack_call_pending_DSRs: | |
| 685 stmfd sp!,{r4,r5,lr} | |
| 686 // Disable interrupts | |
| 687 mrs r4,cpsr // disable IRQ's | |
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688 orr r2,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
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689 bic r5,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
| 2 | 690 msr cpsr,r2 |
| 691 // Switch to interrupt stack | |
| 692 mov r3,sp // save old stack pointer | |
| 693 ldr sp,.__interrupt_stack | |
| 694 stmfd sp!,{r3} // stored at top of interrupt stack | |
| 695 ldr r2,.irq_level // current number of nested interrupts | |
| 696 ldr r3,[r2] | |
| 697 add r3,r3,#1 // bump nesting level | |
| 698 str r3,[r2] | |
| 699 msr cpsr,r5 // enable interrupts | |
| 700 | |
| 701 bl cyg_interrupt_call_pending_DSRs | |
| 702 | |
| 703 // Disable interrupts | |
| 704 mrs r1,cpsr // disable IRQ's | |
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705 orr r2,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
| 2 | 706 msr cpsr,r2 |
| 707 | |
| 708 // Move back to the thread stack. | |
| 709 ldr r2,.irq_level | |
| 710 ldr r3,[r2] | |
| 711 sub r3,r3,#1 // decrement nesting level | |
| 712 str r3,[r2] | |
| 713 ldr sp,[sp] // This should be the saved stack pointer | |
| 714 msr cpsr,r4 // restore interrupts to original state | |
| 715 | |
| 716 ldmfd sp!,{r4,r5,pc} // return | |
| 717 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
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718 |
| 2 | 719 |
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720 // Dummy/support functions |
| 2 | 721 |
| 722 .global __gccmain | |
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723 .global _psr |
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724 .global _sp |
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725 |
| 2 | 726 __gccmain: |
| 727 mov pc,lr | |
| 728 | |
| 729 _psr: | |
| 730 mrs r0,cpsr | |
| 731 mov pc,lr | |
| 732 | |
| 733 _sp: | |
| 734 mov r0,sp | |
| 735 mov pc,lr | |
| 736 | |
| 737 | |
| 738 // | |
| 739 // Pointers to various objects. | |
| 740 // | |
| 741 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 742 PTR(__GDB_stack_base) | |
| 743 PTR(__GDB_stack) | |
| 744 #endif | |
| 745 PTR(__startup_stack) | |
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746 PTR(__FIQ_exception_stack) |
| 2 | 747 PTR(__exception_stack) |
| 748 PTR(__undef_exception_stack) | |
| 749 PTR(__bss_start) | |
| 750 PTR(__bss_end) | |
| 751 PTR(_end) | |
| 752 PTR(__rom_data_start) | |
| 753 PTR(__ram_data_start) | |
| 754 PTR(__ram_data_end) | |
| 755 PTR(hal_interrupt_handlers) | |
| 756 PTR(hal_interrupt_data) | |
| 757 PTR(hal_interrupt_objects) | |
| 758 PTR(__exception_handlers) | |
| 759 PTR(init_flag) | |
| 760 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 761 PTR(cyg_scheduler_sched_lock) | |
| 762 #endif | |
| 763 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 764 PTR(irq_level) | |
| 765 PTR(__interrupt_stack) | |
| 766 #endif | |
| 767 | |
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768 // |
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769 // Identification - useful to find out when a system was configured |
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770 _eCos_id: |
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771 .asciz "eCos : " __DATE__ |
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772 |
| 2 | 773 |
| 774 // ------------------------------------------------------------------------- | |
| 775 // Interrupt vector tables. | |
| 776 // These tables contain the isr, data and object pointers used to deliver | |
| 777 // interrupts to user code. | |
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778 |
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779 // Despite appearances, their sizes are not #defines, but .equ symbols |
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780 // generated by magic without proper dependencies in arm.inc |
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781 // Recompiling will not DTRT without manual intervention. |
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782 |
| 2 | 783 .data |
| 784 | |
| 785 init_flag: | |
| 786 .long 0 | |
| 787 | |
| 788 .extern hal_default_isr | |
| 789 | |
| 790 .globl hal_interrupt_handlers | |
| 791 hal_interrupt_handlers: | |
| 792 .rept CYGNUM_HAL_ISR_COUNT | |
| 793 .long hal_default_isr | |
| 794 .endr | |
| 795 | |
| 796 .globl hal_interrupt_data | |
| 797 hal_interrupt_data: | |
| 798 .rept CYGNUM_HAL_ISR_COUNT | |
| 799 .long 0 | |
| 800 .endr | |
| 801 | |
| 802 .globl hal_interrupt_objects | |
| 803 hal_interrupt_objects: | |
| 804 .rept CYGNUM_HAL_ISR_COUNT | |
| 805 .long 0 | |
| 806 .endr | |
| 807 | |
| 808 // ------------------------------------------------------------------------- | |
| 809 // Temporary interrupt stack | |
| 810 | |
| 811 .section ".bss" | |
| 812 | |
| 813 // Small stacks, only used for saving information between CPU modes | |
| 814 __exception_stack_base: | |
| 815 .rept 32 | |
| 816 .long 0 | |
| 817 .endr | |
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818 __FIQ_exception_stack: |
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819 .rept 32 |
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820 .long 0 |
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821 .endr |
| 2 | 822 __exception_stack: |
| 823 .rept 32 | |
| 824 .long 0 | |
| 825 .endr | |
| 826 __undef_exception_stack: | |
| 827 | |
| 828 // Runtime stack used during all interrupt processing | |
| 829 #ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 830 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 | |
| 831 #endif | |
| 832 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 833 .balign 16 | |
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834 .global cyg_interrupt_stack_base |
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835 cyg_interrupt_stack_base: |
| 2 | 836 __interrupt_stack_base: |
| 837 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 838 .byte 0 | |
| 839 .endr | |
| 840 .balign 16 | |
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841 .global cyg_interrupt_stack |
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842 cyg_interrupt_stack: |
| 2 | 843 __interrupt_stack: |
| 844 irq_level: | |
| 845 .long 0 | |
| 846 #endif | |
| 847 | |
| 848 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 849 .balign 16 | |
| 850 __GDB_stack_base: | |
| 851 .rept 0x400 | |
| 852 .byte 0 | |
| 853 .endr | |
| 854 __GDB_stack: | |
| 855 #endif | |
| 856 .balign 16 | |
| 857 __startup_stack_base: | |
| 858 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 859 .rept 512 | |
| 860 #else | |
| 861 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 862 #endif | |
| 863 .byte 0 | |
| 864 .endr | |
| 865 .balign 16 | |
| 866 __startup_stack: | |
| 867 | |
|
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868 #ifdef PLATFORM_EXTRAS |
|
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869 #include PLATFORM_EXTRAS |
|
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870 #endif |
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871 |
| 2 | 872 // -------------------------------------------------------------------------- |
| 873 // end of vectors.S |