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annotate packages/hal/powerpc/ppc40x/current/include/var_cache.h @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents 8d6df59beb34
children
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3 //=============================================================================
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4 //
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5 // var_cache.h
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6 //
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7 // Variant HAL cache control API
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8 //
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9 //=============================================================================
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10 // ####ECOSGPLCOPYRIGHTBEGIN####
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11 // -------------------------------------------
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12 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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14 //
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15 // eCos is free software; you can redistribute it and/or modify it under
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16 // the terms of the GNU General Public License as published by the Free
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17 // Software Foundation; either version 2 or (at your option) any later
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18 // version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT
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21 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License
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26 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use
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30 // macros or inline functions from this file, or you compile this file
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31 // and link it with other works to produce a work based on this file,
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32 // this file does not by itself cause the resulting work to be covered by
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33 // the GNU General Public License. However the source code for this file
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34 // must still be made available in accordance with section (3) of the GNU
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35 // General Public License v2.
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36 //
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37 // This exception does not invalidate any other reasons why a work based
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38 // on this file might be covered by the GNU General Public License.
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39 // -------------------------------------------
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40 // ####ECOSGPLCOPYRIGHTEND####
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41 //=============================================================================
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42 //#####DESCRIPTIONBEGIN####
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43 //
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44 // Author(s): nickg
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45 // Contributors:nickg, jskov
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46 // Date: 2000-04-02
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47 // Purpose: Variant cache control API
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48 // Description: The macros defined here provide the HAL APIs for handling
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49 // cache control operations on the PPC60x variant CPUs.
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50 // Usage: Is included via the architecture cache header:
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51 // #include <cyg/hal/hal_cache.h>
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52 // ...
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53 //
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54 //####DESCRIPTIONEND####
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55 //
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56 //=============================================================================
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57
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58 #include <pkgconf/hal.h>
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59 #include <cyg/infra/cyg_type.h>
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60
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61 #include <cyg/hal/ppc_regs.h>
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62
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63 #include <cyg/hal/plf_cache.h>
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64
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65
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66 //-----------------------------------------------------------------------------
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67 // Cache dimensions
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68
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69 #if defined(CYGHWR_HAL_POWERPC_PPC4XX_403)
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70 // Data cache
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71 #define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes
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72 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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73 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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74
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75 // Instruction cache
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76 #define HAL_ICACHE_SIZE 16384 // Size of cache in bytes
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77 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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78 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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79 #endif // 403
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80
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81 #if defined(CYGHWR_HAL_POWERPC_PPC4XX_405) || defined(CYGHWR_HAL_POWERPC_PPC4XX_405GP) || defined(CYGHWR_HAL_POWERPC_PPC4XX_405EP)
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82 // Data cache
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83 #define HAL_DCACHE_SIZE (16*1024) // Size of data cache in bytes
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84 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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85 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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86
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87 // Instruction cache
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88 #define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
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89 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
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90 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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91 #endif // 405
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92
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93 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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94 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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95
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96 //-----------------------------------------------------------------------------
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97 // Global control of data cache
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98
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99 // Enable the data cache - this is implicit whenever the MMU is turned on
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100 #define HAL_DCACHE_ENABLE()
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101
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102 // Disable the data cache
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103 #define HAL_DCACHE_DISABLE()
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104
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105 // Invalidate the entire cache
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106 #define HAL_DCACHE_INVALIDATE_ALL() \
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107 CYG_MACRO_START \
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108 int _i_, _ix_, _indx_; \
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109 _indx_ = 0; \
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110 _ix_ = HAL_DCACHE_SIZE/2; \
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111 for (_i_ = 0; _i_ < HAL_DCACHE_SETS; _i_++) { \
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112 asm volatile ("dccci 0,%0;" :: "r"(_indx_)); \
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113 asm volatile ("dccci %1,%0;" :: "r"(_indx_), "r"(_ix_)); \
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114 _indx_ += HAL_DCACHE_LINE_SIZE; \
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115 } \
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116 CYG_MACRO_END
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117
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118 #if 0
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119 // Synchronize the contents of the cache with memory.
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120 #define HAL_DCACHE_SYNC() \
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121 CYG_MACRO_START \
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122 int _indx_; \
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123 for (_indx_ = 0; _indx_ < HAL_DCACHE_SIZE; _indx_ += HAL_DCACHE_LINE_SIZE) { \
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124 asm volatile ("dcbf 0,%0;" :: "r"(_indx_)); \
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125 } \
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126 CYG_MACRO_END
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127 #else
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128 // Synchronize the contents of the cache with memory.
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129 #define HAL_DCACHE_SYNC() \
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130 CYG_MACRO_START \
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131 cyg_int32 i; \
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132 cyg_uint32 *__base = (cyg_uint32 *) (0); \
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133 /* for (i = 0; i < HAL_DCACHE_SIZE; i += sizeof(cyg_uint32)) { */ \
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134 for (i = 0; i < (HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); i++, __base += HAL_DCACHE_LINE_SIZE/4){\
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135 asm volatile ("lwz %%r0,0(%0)" : : "r" (__base) : "r0"); \
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136 } \
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137 CYG_MACRO_END
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138 #endif
134
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139
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140 // Query the state of the data cache
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141 #define HAL_DCACHE_IS_ENABLED(_state_) \
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142 CYG_MACRO_START \
136
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143 (_state_) = 1; \
134
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144 CYG_MACRO_END
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145
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146 // Set the data cache refill burst size
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147 //#define HAL_DCACHE_BURST_SIZE(_size_)
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148
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149 // Set the data cache write mode
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150 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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151
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152 //#define HAL_DCACHE_WRITETHRU_MODE 0
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153 //#define HAL_DCACHE_WRITEBACK_MODE 1
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154
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155 // Load the contents of the given address range into the data cache
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156 // and then lock the cache so that it stays there.
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157 //#define HAL_DCACHE_LOCK(_base_, _size_)
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158
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159 // Undo a previous lock operation
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160 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
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161
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162 // Unlock entire cache
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163 #define HAL_DCACHE_UNLOCK_ALL()
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164
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165 //-----------------------------------------------------------------------------
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166 // Data cache line control
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167
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168 // Allocate cache lines for the given address range without reading its
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169 // contents from memory.
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170 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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171
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172 // Write dirty cache lines to memory and invalidate the cache entries
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173 // for the given address range.
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174 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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175 CYG_MACRO_START \
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176 cyg_uint32 __base = (cyg_uint32) (_base_); \
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177 cyg_int32 __size = (cyg_int32) (_size_); \
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178 while (__size > 0) { \
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179 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \
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180 __base += HAL_DCACHE_LINE_SIZE; \
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181 __size -= HAL_DCACHE_LINE_SIZE; \
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182 } \
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183 CYG_MACRO_END
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184
134
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185 // Invalidate cache lines in the given range without writing to memory.
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186 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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187 CYG_MACRO_START \
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188 cyg_uint32 __base = (cyg_uint32) (_base_); \
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189 cyg_int32 __size = (cyg_int32) (_size_); \
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190 while (__size > 0) { \
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191 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \
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192 __base += HAL_DCACHE_LINE_SIZE; \
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193 __size -= HAL_DCACHE_LINE_SIZE; \
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194 } \
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195 CYG_MACRO_END
134
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196
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197 // Write dirty cache lines to memory for the given address range.
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198 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
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199 CYG_MACRO_START \
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200 cyg_uint32 __base = (cyg_uint32) (_base_); \
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201 cyg_int32 __size = (cyg_int32) (_size_); \
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202 while (__size > 0) { \
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203 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \
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204 __base += HAL_DCACHE_LINE_SIZE; \
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205 __size -= HAL_DCACHE_LINE_SIZE; \
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206 } \
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207 CYG_MACRO_END
134
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208
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209 // Preread the given range into the cache with the intention of reading
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210 // from it later.
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211 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \
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212 CYG_MACRO_START \
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213 cyg_uint32 __base = (cyg_uint32) (_base_); \
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214 cyg_int32 __size = (cyg_int32) (_size_); \
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215 while (__size > 0) { \
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216 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \
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217 __base += HAL_DCACHE_LINE_SIZE; \
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218 __size -= HAL_DCACHE_LINE_SIZE; \
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219 } \
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220 CYG_MACRO_END
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221
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222 // Preread the given range into the cache with the intention of writing
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223 // to it later.
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224 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \
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225 CYG_MACRO_START \
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226 cyg_uint32 __base = (cyg_uint32) (_base_); \
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227 cyg_int32 __size = (cyg_int32) (_size_); \
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228 while (__size > 0) { \
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229 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \
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230 __base += HAL_DCACHE_LINE_SIZE; \
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231 __size -= HAL_DCACHE_LINE_SIZE; \
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232 } \
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233 CYG_MACRO_END
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234
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235 // Allocate and zero the cache lines associated with the given range.
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236 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \
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237 CYG_MACRO_START \
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238 cyg_uint32 __base = (cyg_uint32) (_base_); \
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239 cyg_int32 __size = (cyg_int32) (_size_); \
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240 while (__size > 0) { \
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241 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \
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242 __base += HAL_DCACHE_LINE_SIZE; \
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243 __size -= HAL_DCACHE_LINE_SIZE; \
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244 } \
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245 CYG_MACRO_END
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246
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247 //-----------------------------------------------------------------------------
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248 // Global control of Instruction cache
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249
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250 // Enable the instruction cache
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251 #define HAL_ICACHE_ENABLE()
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252
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253 // Disable the instruction cache
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254 #define HAL_ICACHE_DISABLE()
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255
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256 // Invalidate the entire cache
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257 #define HAL_ICACHE_INVALIDATE_ALL() \
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258 CYG_MACRO_START \
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259 int _i_, _indx_; \
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260 _indx_ = 0; \
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261 for (_i_ = 0; _i_ < HAL_ICACHE_SETS; _i_++) { \
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262 asm volatile ("iccci 0,%0;" :: "r"(_indx_)); \
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263 _indx_ += HAL_ICACHE_LINE_SIZE; \
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264 } \
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265 CYG_MACRO_END
134
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266
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267 // Synchronize the contents of the cache with memory.
136
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268 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
134
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269
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270 // Query the state of the instruction cache
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271 #define HAL_ICACHE_IS_ENABLED(_state_) \
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272 CYG_MACRO_START \
136
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273 (_state_) = 1; \
134
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274 CYG_MACRO_END
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275
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276 // Set the instruction cache refill burst size
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277 //#define HAL_ICACHE_BURST_SIZE(_size_)
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278
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279 // Load the contents of the given address range into the instruction cache
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280 // and then lock the cache so that it stays there.
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281 //#define HAL_ICACHE_LOCK(_base_, _size_)
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282
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283 // Undo a previous lock operation
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284 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
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285
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286 // Unlock entire cache
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287 #define HAL_ICACHE_UNLOCK_ALL()
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288
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289 //-----------------------------------------------------------------------------
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290 // Instruction cache line control
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291
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292 // Invalidate cache lines in the given range without writing to memory.
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293 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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294
1223
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295 #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU
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296 // Map a RAM address to a non-cached mirror
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297 #define CYGARC_UNCACHED_ADDRESS(p) ((unsigned long)(p) | 0x80000000)
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298 #else
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299 #define CYGARC_UNCACHED_ADDRESS(p) (p)
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300 #endif
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301
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302 //-----------------------------------------------------------------------------
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303 #endif // ifndef CYGONCE_VAR_CACHE_H
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304 // End of var_cache.h