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annotate packages/hal/powerpc/arch/current/src/hal_misc.c @ 62:7a6ac9edc838 ecos-sw-2000-01-24

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Merge from eCos master repository on 2000-01-24-19:43:49-GMT
author jlarmour
date Mon, 24 Jan 2000 21:43:17 +0000
parents 797268ecc331
children c38311975d4f
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1 //==========================================================================
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2 //
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3 // hal_misc.c
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4 //
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5 // HAL miscellaneous functions
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6 //
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7 //==========================================================================
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8 //####COPYRIGHTBEGIN####
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9 //
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10 // -------------------------------------------
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11 // The contents of this file are subject to the Cygnus eCos Public License
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12 // Version 1.0 (the "License"); you may not use this file except in
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13 // compliance with the License. You may obtain a copy of the License at
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14 // http://sourceware.cygnus.com/ecos
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15 //
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16 // Software distributed under the License is distributed on an "AS IS"
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
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18 // License for the specific language governing rights and limitations under
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19 // the License.
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20 //
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21 // The Original Code is eCos - Embedded Cygnus Operating System, released
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22 // September 30, 1998.
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23 //
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24 // The Initial Developer of the Original Code is Cygnus. Portions created
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25 // by Cygnus are Copyright (C) 1998, 1999 Cygnus Solutions.
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26 // All Rights Reserved.
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27 // -------------------------------------------
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28 //
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29 //####COPYRIGHTEND####
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30 //==========================================================================
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31 //#####DESCRIPTIONBEGIN####
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32 //
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33 // Author(s): nickg, jskov
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34 // Contributors: nickg, jskov,
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35 // jlarmour
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36 // Date: 1999-02-20
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37 // Purpose: HAL miscellaneous functions
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38 // Description: This file contains miscellaneous functions provided by the
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39 // HAL.
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40 //
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41 //####DESCRIPTIONEND####
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42 //
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43 //===========================================================================
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44
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45 #include <pkgconf/hal.h>
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46
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47 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
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48 #include <cyg/hal/ppc_regs.h> // SPR definitions
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49
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50 #include <cyg/infra/cyg_type.h>
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51 #include <cyg/infra/cyg_trac.h> // tracing macros
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52 #include <cyg/infra/cyg_ass.h> // assertion macros
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53 #include <cyg/infra/diag.h> // diag_printf
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54
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55 #include <cyg/hal/hal_arch.h> // HAL header
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56 #include <cyg/hal/hal_cache.h> // HAL cache
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57 #if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
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58 defined(CYGPKG_HAL_EXCEPTIONS)
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59 # include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions
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60 #endif
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61
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62 //---------------------------------------------------------------------------
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63 // Functions used during initialization.
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64
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65 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
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66 cyg_bool cyg_hal_stop_constructors;
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67 #endif
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68
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69 typedef void (*pfunc) (void);
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70 extern pfunc __CTOR_LIST__[];
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71 extern pfunc __CTOR_END__[];
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72
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73 void
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74 cyg_hal_invoke_constructors (void)
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75 {
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76 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
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77 static pfunc *p = &__CTOR_END__[-1];
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78
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79 cyg_hal_stop_constructors = 0;
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80 for (; p >= __CTOR_LIST__; p--) {
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81 (*p) ();
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82 if (cyg_hal_stop_constructors) {
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83 p--;
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84 break;
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85 }
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86 }
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87 #else
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88 pfunc *p;
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89
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90 for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
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91 (*p) ();
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92 #endif
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93 }
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94
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95 // Override any __eabi the compiler might generate. We don't want
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96 // constructors to be called twice.
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97 void __eabi (void) {}
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98
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99 //---------------------------------------------------------------------------
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100 // First level C exception handler.
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101
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102 externC void __handle_exception (void);
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103
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104 externC HAL_SavedRegisters *_hal_registers;
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105
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106 externC void *__mem_fault_handler;
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107
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108 void
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109 cyg_hal_exception_handler(HAL_SavedRegisters *regs)
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110 {
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111 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
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112
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113 // If we caught an exception inside the stubs, see if we were expecting it
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114 // and if so jump to the saved address
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115 if (__mem_fault_handler) {
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116 regs->pc = (CYG_ADDRWORD)__mem_fault_handler;
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117 return; // Caught an exception inside stubs
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118 }
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119
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120 // Set the pointer to the registers of the current exception
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121 // context. At entry the GDB stub will expand the
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122 // HAL_SavedRegisters structure into a (bigger) register array.
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123 _hal_registers = regs;
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124
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125 __handle_exception();
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126
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127 #ifdef CYGPKG_HAL_QUICC
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128 {
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129 // This is unpleasant: it appears that if we interrupt the board
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130 // using ^C coming in on the QUICC's SMC1, by planting a breakpoint
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131 // at the interrupt return address, the decrementer interrupt is
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132 // not taken when the bp exception returns AND WORSE no other
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133 // interrupt is possible until the decrementer fires again. This
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134 // does not apply to simple "incoming character" interrupts; it
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135 // seems it has to be combined with an immediate trap on RTI for
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136 // this to occur.
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137 //
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138 // The solution is to test for decrementer underflow after the
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139 // (any) exception, and maybe reinitialize the decrementer. If the
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140 // decrementer interrupt gets taken, that causes decrementer reinit
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141 // too, and no harm is done.
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142
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143 cyg_uint32 result;
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144 asm volatile(
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145 "mfdec %0;"
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146 : "=r"(result)
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147 );
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148
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149 if ( CYGNUM_HAL_RTC_PERIOD < result ) {
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150 // then we missed a tick, but the exception masked it
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151 // reset the decrementer here
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152 asm volatile(
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153 "mtdec %0;"
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154 : : "r"(CYGNUM_HAL_RTC_PERIOD)
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155 );
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156 }
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157 }
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158 #endif
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159
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160 #elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
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161 defined(CYGPKG_HAL_EXCEPTIONS)
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162 int vector = regs->vector>>8;
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163
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164 // We should decode the vector and pass a more appropriate
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165 // value as the second argument. For now we simply pass a
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166 // pointer to the saved registers. We should also divert
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167 // breakpoint and other debug vectors into the debug stubs.
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168
2
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169 if (vector==CYGNUM_HAL_VECTOR_PROGRAM) {
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170 int srr1;
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171 CYGARC_MFSPR(CYGARC_REG_SRR1, srr1); // get srr1
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172
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173 switch ((srr1 >> 17) & 0xf) {
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174 case 1:
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175 vector = CYGNUM_HAL_EXCEPTION_TRAP;
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176 break;
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177 case 2:
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178 vector = CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION;
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179 break;
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180 case 4:
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181 vector = CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION;
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182 break;
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183 case 8:
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184 vector = CYGNUM_HAL_EXCEPTION_FPU;
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185 break;
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186 default:
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187 CYG_FAIL("Unknown PROGRAM exception!!");
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188 }
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189 }
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190 cyg_hal_deliver_exception( vector, (CYG_ADDRWORD)regs );
0
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191
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192 #else
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193
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194 CYG_FAIL("Exception!!!");
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195
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196 #endif
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197
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198 return;
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199 }
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200
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201 //---------------------------------------------------------------------------
14
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202 // Default ISRs
0
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203
2
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204 externC cyg_uint32
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205 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
0
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206 {
2
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207 diag_printf("Interrupt: %d\n", vector);
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208
0
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209 CYG_FAIL("Spurious Interrupt!!!");
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210 return 0;
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211 }
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212
14
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213 // The decrementer default ISR has to do nothing. The reason is that
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214 // decrementer interrupts cannot be disabled - if a kernel configuration
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215 // does not use the RTC, but does use external interrupts, the decrementer
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216 // underflow could cause a CYG_FAIL (as above) even though the user did
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217 // not expect any decrementer interrupts to happen.
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218 externC cyg_uint32
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219 hal_default_decrementer_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
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220 {
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221 return 0;
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diff changeset
222 }
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223
0
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224 //---------------------------------------------------------------------------
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225 // Idle thread action
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226
2
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diff changeset
227 void
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228 hal_idle_thread_action( cyg_uint32 count )
0
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229 {
32
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230 #if 0
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231 #ifdef CYG_HAL_POWERPC_MPC860
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232 register cyg_uint32 result;
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diff changeset
233
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234 cyg_uint32 *psivec = (cyg_uint32*)CYGARC_REG_IMM_SIVEC ;
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235 cyg_uint32 *psimask = (cyg_uint32*)CYGARC_REG_IMM_SIMASK;
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236 cyg_uint32 *psipend = (cyg_uint32*)CYGARC_REG_IMM_SIPEND;
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237 cyg_uint16 *ptbscr = (cyg_uint16*)CYGARC_REG_IMM_TBSCR;
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diff changeset
238
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diff changeset
239 asm volatile(
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240 "mfdec %0;"
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241 : "=r"(result)
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diff changeset
242 );
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243 diag_printf( "Dec %08x, TBSCR %04x, vec %d: sivec %08x, simask %08x, sipend %08x\n",
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244 result, (cyg_uint32)(*ptbscr), (*psivec)>>26, *psivec, *psimask, *psipend );
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diff changeset
245 #endif
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246 #endif
0
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247 }
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248
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249 //---------------------------------------------------------------------------
2
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250 // Use MMU resources to map memory regions.
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251 // Takes and returns an int used to ID the MMU resource to use. This ID
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252 // is increased as resources are used and should be used for subsequent
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253 // invocations.
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254 static int
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255 hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys,
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256 cyg_int32 size, cyg_uint8 flags)
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257 {
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258 #ifdef CYG_HAL_POWERPC_MPC603
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259 {
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260 // Use BATs to map the memory.
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261 cyg_uint32 ubat, lbat;
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262
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263 ubat = (virt & UBAT_BEPIMASK) | UBAT_VS | UBAT_VP;
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264 lbat = (phys & LBAT_BRPNMASK);
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265 if (flags & CYGARC_MEMDESC_CI)
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266 lbat |= LBAT_I;
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267 if (flags & CYGARC_MEMDESC_GUARDED)
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268 lbat |= LBAT_G;
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269
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270 // There are 4 BATs, size is programmable.
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271 while (id < 4 && size > 0) {
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272 cyg_uint32 blk_size = 128*1024;
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273 cyg_uint32 bl = 0;
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274 while (blk_size < 256*1024*1024 && blk_size < size) {
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275 blk_size *= 2;
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276 bl = (bl << 1) | 1;
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diff changeset
277 }
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278 ubat = (ubat & ~UBAT_BLMASK) | (bl << 2);
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279
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280 switch (id) {
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281 case 0:
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282 CYGARC_MTSPR (IBAT0U, ubat);
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283 CYGARC_MTSPR (IBAT0L, lbat);
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284 CYGARC_MTSPR (DBAT0U, ubat);
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285 CYGARC_MTSPR (DBAT0L, lbat);
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286 break;
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diff changeset
287 case 1:
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288 CYGARC_MTSPR (IBAT1U, ubat);
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289 CYGARC_MTSPR (IBAT1L, lbat);
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290 CYGARC_MTSPR (DBAT1U, ubat);
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291 CYGARC_MTSPR (DBAT1L, lbat);
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292 break;
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diff changeset
293 case 2:
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294 CYGARC_MTSPR (IBAT2U, ubat);
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diff changeset
295 CYGARC_MTSPR (IBAT2L, lbat);
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296 CYGARC_MTSPR (DBAT2U, ubat);
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297 CYGARC_MTSPR (DBAT2L, lbat);
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diff changeset
298 break;
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diff changeset
299 case 3:
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300 CYGARC_MTSPR (IBAT3U, ubat);
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301 CYGARC_MTSPR (IBAT3L, lbat);
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302 CYGARC_MTSPR (DBAT3U, ubat);
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303 CYGARC_MTSPR (DBAT3L, lbat);
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diff changeset
304 break;
443894e2e912 Block commit of eCos version 1.2.1
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diff changeset
305 }
443894e2e912 Block commit of eCos version 1.2.1
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306
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307 size -= blk_size;
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308 id++;
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diff changeset
309 }
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diff changeset
310 }
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311 #endif
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312
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313
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314 #ifdef CYG_HAL_POWERPC_MPC8xx
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315 {
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316 // The MPC8xx CPUs do not have BATs. Fortunately we don't
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317 // currently use the MMU, so we can simulate BATs by using the
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318 // TLBs.
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319
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320 cyg_uint32 epn, rpn, ctr, twc;
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321 int max_tlbs;
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322
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323 #if defined(CYG_HAL_POWERPC_MPC860)
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324 // There are 32 TLBs.
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325 max_tlbs = 32;
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326 #endif
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327 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850)
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328 // There are 8 TLBs.
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329 max_tlbs = 8;
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330 #endif
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331
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332 epn = (virt & MI_EPN_EPNMASK) | MI_EPN_EV;
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333 rpn = ((phys & MI_RPN_RPNMASK)
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334 | MI_RPN_PPRWRW | MI_RPN_LPS | MI_RPN_SH | MI_RPN_V);
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335 if (flags & CYGARC_MEMDESC_CI)
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336 rpn |= MI_RPN_CI;
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337
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338 twc = MI_TWC_PS8MB | MI_TWC_V;
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339 if (flags & CYGARC_MEMDESC_GUARDED)
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340 twc |= MI_TWC_G;
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341
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diff changeset
342 // Ignore attempts to use more than max_tlbs.
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343 while (id < max_tlbs && size > 0) {
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344 ctr = id << MI_CTR_INDX_SHIFT;
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345
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346 // Instruction TLB.
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347 CYGARC_MTSPR (MI_TWC, twc);
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348 CYGARC_MTSPR (MI_CTR, ctr);
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349 CYGARC_MTSPR (MI_EPN, epn);
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350 CYGARC_MTSPR (MI_RPN, rpn);
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351
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diff changeset
352 // Data TLB.
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353 {
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354 cyg_uint32 drpn;
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355
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diff changeset
356 // Need to mark data page as changed or an exception
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357 // will be generated on first write to the page.
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358 drpn = rpn | MD_RPN_CHANGED;
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359
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360 CYGARC_MTSPR (MD_TWC, twc);
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361 CYGARC_MTSPR (MD_CTR, ctr);
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362 CYGARC_MTSPR (MD_EPN, epn);
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363 CYGARC_MTSPR (MD_RPN, drpn);
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364 }
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365
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366 // Move to next 8MB block.
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367 size -= 8*1024*1024;
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368 epn += 8*1024*1024;
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369 rpn += 8*1024*1024;
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370 id++;
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371 }
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372 }
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373 #endif
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374
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375 return id;
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376 }
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377
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diff changeset
378
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diff changeset
379 // Initialize MMU to a sane (NOP) state.
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380 static void
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381 hal_clear_MMU (void)
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382 {
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383 #ifdef CYG_HAL_POWERPC_MPC603
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384 {
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385 cyg_uint32 ubat, lbat;
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386
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387 // Initialize BATs with 0 -- VS&VP are unset, making all matches fail
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388 ubat = 0;
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389 lbat = 0;
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390
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391 CYGARC_MTSPR (IBAT0U, ubat);
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392 CYGARC_MTSPR (IBAT0L, lbat);
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393 CYGARC_MTSPR (DBAT0U, ubat);
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diff changeset
394 CYGARC_MTSPR (DBAT0L, lbat);
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diff changeset
395 CYGARC_MTSPR (IBAT1U, ubat);
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396 CYGARC_MTSPR (IBAT1L, lbat);
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397 CYGARC_MTSPR (DBAT1U, ubat);
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398 CYGARC_MTSPR (DBAT1L, lbat);
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diff changeset
399 CYGARC_MTSPR (IBAT2U, ubat);
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400 CYGARC_MTSPR (IBAT2L, lbat);
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401 CYGARC_MTSPR (DBAT2U, ubat);
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402 CYGARC_MTSPR (DBAT2L, lbat);
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diff changeset
403 CYGARC_MTSPR (IBAT3U, ubat);
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404 CYGARC_MTSPR (IBAT3L, lbat);
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405 CYGARC_MTSPR (DBAT3U, ubat);
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406 CYGARC_MTSPR (DBAT3L, lbat);
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diff changeset
407 }
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408 #endif
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409
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410 #ifdef CYG_HAL_POWERPC_MPC8xx
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411 {
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412 // Initialize TLBs with 0, Valid bits unset.
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413
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414 cyg_uint32 ctr;
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415 int id;
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416 int max_tlbs;
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417
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418 #if defined(CYG_HAL_POWERPC_MPC860)
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419 // There are 32 TLBs.
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420 max_tlbs = 32;
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421 #endif
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422 #if defined(CYG_HAL_POWERPC_MPC823) || defined(CYG_HAL_POWERPC_MPC850)
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423 // There are 8 TLBs.
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424 max_tlbs = 8;
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diff changeset
425 #endif
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426
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427 CYGARC_MTSPR (M_CASID, 0);
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428
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429 for (id = 0; id < max_tlbs; id++) {
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430 ctr = id << MI_CTR_INDX_SHIFT;
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431
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diff changeset
432 // Instruction TLBs.
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433 CYGARC_MTSPR (MI_TWC, 0);
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434 CYGARC_MTSPR (MI_CTR, ctr);
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435 CYGARC_MTSPR (MI_EPN, 0);
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436 CYGARC_MTSPR (MI_RPN, 0);
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diff changeset
437 // Data TLBs.
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diff changeset
438 CYGARC_MTSPR (MD_TWC, 0);
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439 CYGARC_MTSPR (MD_CTR, ctr);
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440 CYGARC_MTSPR (MD_EPN, 0);
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441 CYGARC_MTSPR (MD_RPN, 0);
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diff changeset
442 }
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diff changeset
443 }
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444 #endif
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445 }
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446
16
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diff changeset
447 // NB this demands that the platform HAL has provided an
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST
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diff changeset
448 // externC cyg_memdesc_t cyg_hal_mem_map[];
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diff changeset
449 // as detailed in hal_cache.h:
2
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diff changeset
450 externC void hal_MMU_init (void)
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451 {
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diff changeset
452 int id = 0;
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diff changeset
453 int i = 0;
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454
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diff changeset
455 hal_clear_MMU ();
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456
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diff changeset
457 while (cyg_hal_mem_map[i].size) {
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458 id = hal_map_memory (id,
443894e2e912 Block commit of eCos version 1.2.1
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459 cyg_hal_mem_map[i].virtual_addr,
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diff changeset
460 cyg_hal_mem_map[i].physical_addr,
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461 cyg_hal_mem_map[i].size,
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462 cyg_hal_mem_map[i].flags);
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463 i++;
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diff changeset
464 }
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diff changeset
465 }
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466
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467 //---------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1
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diff changeset
468 // Initial cache enabling
18
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diff changeset
469
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diff changeset
470 // These are "indirected" to make it easier to support other platform
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diff changeset
471 // variants in the future:
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diff changeset
472
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diff changeset
473 #ifdef CYGPKG_HAL_POWERPC_COGENT
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diff changeset
474 # define CYGPRI_INIT_CACHES 1
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diff changeset
475 # ifdef CYG_HAL_STARTUP_RAM
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diff changeset
476 # define CYGPRI_ENABLE_CACHES 1
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diff changeset
477 # endif
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diff changeset
478 #endif
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diff changeset
479
32
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diff changeset
480 #ifdef CYGPKG_HAL_POWERPC_MBX // Enable all caches for MBX860
62
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diff changeset
481 # ifndef CYGSEM_HAL_ROM_MONITOR // unless we are making a stub rom
32
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diff changeset
482 # define CYGPRI_INIT_CACHES 1
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diff changeset
483 # define CYGPRI_ENABLE_CACHES 1
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diff changeset
484 # endif
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diff changeset
485 #endif
18
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diff changeset
486
46
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diff changeset
487
18
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diff changeset
488 // Do not enable caches for the FADS port pro tem; the memory mapping is
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diff changeset
489 // not set up.
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diff changeset
490
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diff changeset
491 // Do not enable caches for the simulator, it just slows it down.
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diff changeset
492
2
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diff changeset
493 externC void
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diff changeset
494 hal_enable_caches(void)
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diff changeset
495 {
18
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diff changeset
496 #ifdef CYGPRI_INIT_CACHES
2
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diff changeset
497 // Initialize caches.
443894e2e912 Block commit of eCos version 1.2.1
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diff changeset
498 HAL_ICACHE_UNLOCK_ALL();
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diff changeset
499 HAL_DCACHE_UNLOCK_ALL();
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diff changeset
500 HAL_ICACHE_INVALIDATE_ALL();
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diff changeset
501 HAL_DCACHE_INVALIDATE_ALL();
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502
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503 // Enable caches.
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504 #ifdef CYGPRI_ENABLE_CACHES
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505 // Cogent board doesn't support burst access to the ROM and on the
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506 // MPC8xx caches require burst.
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507 HAL_ICACHE_ENABLE();
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508 HAL_DCACHE_ENABLE();
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509 #endif
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510 #endif
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511
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512 #ifdef CYG_HAL_POWERPC_MPC8xx
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513 // Disable serialization
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514 {
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515 cyg_uint32 ictrl;
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516 CYGARC_MFSPR (ICTRL, ictrl);
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517 ictrl |= ICTRL_NOSERSHOW;
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518 CYGARC_MTSPR (ICTRL, ictrl);
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519 }
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520 #endif
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521 }
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522
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523 //---------------------------------------------------------------------------
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524 //A jump via a null pointer causes the CPU to end up here.
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525 externC void
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526 hal_null_call()
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527 {
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528
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529 CYG_FAIL("Call via NULL-pointer!");
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530 for(;;);
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531 }
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532
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533 //---------------------------------------------------------------------------
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534 // End of hal_misc.c