Mercurial > ecos
annotate packages/hal/powerpc/arch/current/src/vectors.S @ 2438:8317d1af06db
Optimize system initialization
| author | gthomas |
|---|---|
| date | Fri, 12 Oct 2007 15:30:20 +0000 |
| parents | 3e87cf3554ba |
| children | 73921684f287 |
| rev | line source |
|---|---|
| 2 | 1 ##========================================================================== |
| 0 | 2 ## |
| 3 ## vectors.S | |
| 4 ## | |
| 5 ## PowerPC exception vectors | |
| 6 ## | |
| 2 | 7 ##========================================================================== |
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8 #####ECOSGPLCOPYRIGHTBEGIN#### |
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9 ## ------------------------------------------- |
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10 ## This file is part of eCos, the Embedded Configurable Operating System. |
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
| 423 | 12 ## Copyright (C) 2002 Gary Thomas |
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13 ## |
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14 ## eCos is free software; you can redistribute it and/or modify it under |
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15 ## the terms of the GNU General Public License as published by the Free |
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16 ## Software Foundation; either version 2 or (at your option) any later version. |
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17 ## |
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18 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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19 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 ## for more details. |
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22 ## |
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23 ## You should have received a copy of the GNU General Public License along |
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24 ## with eCos; if not, write to the Free Software Foundation, Inc., |
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25 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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26 ## |
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27 ## As a special exception, if other files instantiate templates or use macros |
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28 ## or inline functions from this file, or you compile this file and link it |
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29 ## with other works to produce a work based on this file, this file does not |
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30 ## by itself cause the resulting work to be covered by the GNU General Public |
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31 ## License. However the source code for this file must still be made available |
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32 ## in accordance with section (3) of the GNU General Public License. |
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33 ## |
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34 ## This exception does not invalidate any other reasons why a work based on |
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35 ## this file might be covered by the GNU General Public License. |
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36 ## |
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37 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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38 ## at http://sources.redhat.com/ecos/ecos-license/ |
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39 ## ------------------------------------------- |
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40 #####ECOSGPLCOPYRIGHTEND#### |
| 2 | 41 ##========================================================================== |
| 0 | 42 #######DESCRIPTIONBEGIN#### |
| 43 ## | |
| 2 | 44 ## Author(s): nickg, jskov |
| 45 ## Contributors: nickg, jskov | |
| 46 ## Date: 1999-02-20 | |
| 47 ## Purpose: PowerPC exception vectors | |
| 48 ## Description: This file defines the code placed into the exception | |
| 49 ## vectors. It also contains the first level default VSRs | |
| 50 ## that save and restore state for both exceptions and | |
| 51 ## interrupts. | |
| 0 | 52 ## |
| 53 ######DESCRIPTIONEND#### | |
| 54 ## | |
| 2 | 55 ##========================================================================== |
| 0 | 56 |
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57 #=========================================================================== |
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58 # |
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59 # The PowerPC exception handling has changed as of version 1.3.1. |
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60 # The primary motivation for rewriting the code was to bring it more |
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61 # in line with the other HALs, in particular to allow a RAM application |
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62 # to cleanly take over only a subset of vectors from a running ROM |
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63 # monitor. |
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64 # |
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65 # GDB stubs (and CygMon, should it be ported to PPC) copies |
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66 # exception vector entry handler code to address 0. These vector entry |
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67 # handlers (defined by the exception_vector macro below) compute |
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68 # a vector index into the hal_vsr_table, fetch the pointer, and |
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69 # jump to the HAL vector service routine (VSR). |
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70 # |
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71 # The hal_vsr_table is located immediately after the vector |
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72 # handlers (at address 0x3000), allowing RAM applications to |
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73 # change VSRs as necessary, while still keeping desired ROM |
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74 # monitor functionality available for debugging. |
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75 # |
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76 # ROM applications can still be configured to leave the vector entry |
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77 # handlers at 0xff000000, but there is at the moment no |
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78 # provision for reclaiming the reserved vector space in RAM to |
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79 # application usage. |
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80 # |
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81 # RAM applications can also be configured to provide exception |
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82 # handlers which are copied to address 0 on startup, thus taking |
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83 # full control of the target. |
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84 # |
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85 # |
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86 # Default configuration is for RAM applications to rely on an |
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87 # existing ROM monitor to provide debugging functionality, and |
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88 # for ROM applications to copy vectors to address 0. |
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89 # |
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90 # |
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91 # Unfortunately the new exception scheme is not compatible with the |
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92 # old scheme. Stubs and applications must be compiled using the same |
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93 # scheme (i.e., old binaries will not run with new stubs, and new |
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94 # binaries will not run with old stubs). |
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95 # |
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96 #=========================================================================== |
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97 |
| 0 | 98 #include <pkgconf/hal.h> |
| 99 | |
| 100 #ifdef CYGPKG_KERNEL | |
| 101 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT | |
| 102 #endif | |
| 2 | 103 |
| 104 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS | |
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105 #include <cyg/hal/ppc_regs.h> |
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106 |
| 2 | 107 #=========================================================================== |
| 0 | 108 |
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109 // .file "vectors.S" |
| 0 | 110 |
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111 .extern hal_interrupt_data |
| 0 | 112 .extern hal_interrupt_handlers |
| 113 .extern hal_interrupt_objects | |
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114 .extern hal_vsr_table |
| 0 | 115 |
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116 .extern cyg_hal_invoke_constructors |
| 0 | 117 .extern cyg_instrument |
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118 .extern cyg_start |
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119 .extern hal_IRQ_init |
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120 .extern hal_MMU_init |
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121 .extern hal_enable_caches |
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122 .extern hal_hardware_init |
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123 .extern initialize_stub |
| 0 | 124 |
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125 .extern __bss_start |
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126 .extern __bss_end |
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127 .extern __sbss_start |
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128 .extern __sbss_end |
| 0 | 129 |
| 2 | 130 #=========================================================================== |
| 0 | 131 # MSR initialization value |
| 132 # zero all bits except: | |
| 133 # FP = floating point available | |
| 134 # ME = machine check enabled | |
| 135 # IP = vectors at 0xFFFxxxxx (ROM startup only) | |
| 2 | 136 # IR = instruction address translation |
| 137 # DR = data address translation | |
| 0 | 138 # RI = recoverable interrupt |
| 139 | |
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140 #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_RI) |
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141 |
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142 #if (CYGHWR_HAL_POWERPC_VECTOR_BASE == 0xfff00000) |
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143 # define IP_BIT MSR_IP |
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144 #else |
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145 # define IP_BIT 0 |
| 0 | 146 #endif |
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147 |
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148 #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU |
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149 # define IR_DR_BITS (MSR_IR | MSR_DR) |
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150 #else |
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151 # define IR_DR_BITS 0 |
| 0 | 152 #endif |
| 153 | |
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154 #define CYG_MSR (CYG_MSR_COMMON | IP_BIT | IR_DR_BITS) |
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155 |
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156 # Include variant macros after MSR definition. |
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157 #include <cyg/hal/arch.inc> |
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158 #include <cyg/hal/ppc_offsets.inc> |
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159 |
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160 |
| 2 | 161 #=========================================================================== |
| 0 | 162 # If the following option is enabled, we only save registers up to R12. |
| 163 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do | |
| 164 # not need to save them when calling C functions. | |
| 165 | |
| 166 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT | |
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167 # define MAX_SAVE_REG 12 |
| 0 | 168 #else |
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169 # define MAX_SAVE_REG 31 |
| 0 | 170 #endif |
| 171 | |
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172 |
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173 #if defined(CYGHWR_HAL_POWERPC_NEED_VECTORS) |
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174 |
| 2 | 175 #=========================================================================== |
| 0 | 176 # Start by defining the exceptions vectors that must be placed at |
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177 # locations 0xFFF00000 or 0x00000000. The following code will normally |
| 0 | 178 # be located at 0xFFF00000 in the ROM. It may optionally be copied out |
| 179 # to 0x00000000 if we want to use the RAM vectors. For this reason this code | |
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180 # MUST BE POSITION INDEPENDENT. |
| 0 | 181 |
| 182 .section ".vectors","ax" | |
| 183 | |
| 2 | 184 #--------------------------------------------------------------------------- |
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185 # Macros for generating an exception vector service routine |
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186 |
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187 # Reset vector macro |
| 0 | 188 |
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189 .macro reset_vector name |
| 0 | 190 .p2align 8 |
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191 .globl __exception_\name |
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192 __exception_\name: |
| 473 | 193 #ifdef CYGSEM_HAL_POWERPC_RESET_USES_JUMP |
| 194 bl _start | |
| 195 #else | |
| 0 | 196 lwi r3,_start |
| 197 mtlr r3 | |
| 198 blr | |
| 473 | 199 #endif |
| 200 | |
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201 .endm |
| 0 | 202 |
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203 # Generic vector macro |
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204 |
| 0 | 205 .macro exception_vector name |
| 206 .p2align 8 | |
| 207 .globl __exception_\name | |
| 208 __exception_\name: | |
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209 mtspr SPRG1,r3 # stash some work registers away |
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210 mtspr SPRG2,r4 |
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211 mtspr SPRG3,r5 |
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212 mfcr r4 # stash CR |
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213 li r5,__exception_\name-rom_vectors # load low half of vector addr |
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214 srwi r5,r5,6 # shift right by 6 |
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215 lwi r3,hal_vsr_table # table base |
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216 lwzx r3,r3,r5 # address of vsr |
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217 mflr r5 # save link register |
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218 mtlr r3 # put vsr address into it |
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219 li r3,__exception_\name-rom_vectors # reload low half of vector addr |
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220 blr # go to common code |
| 0 | 221 .endm |
| 222 | |
| 2 | 223 #--------------------------------------------------------------------------- |
| 0 | 224 # Define the exception vectors. |
| 225 | |
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226 // Some platforms won't let us put the vector code just where we want |
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227 // This macro introduces some lattitude in vector placement |
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228 |
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229 #ifdef CYG_HAL_FUDGE_VECTOR_ALIGNMENT |
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230 hal_fudge_vector_alignment |
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231 #endif |
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232 |
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233 rom_vectors: |
| 0 | 234 # These are the architecture defined vectors that |
| 235 # are always present. | |
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236 #ifdef CYG_HAL_RESERVED_VECTOR_00000 |
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237 hal_reserved_vector_00000 |
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238 #else |
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239 exception_vector reserved_00000 |
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240 #endif |
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241 reset_vector reset |
| 0 | 242 exception_vector machine_check |
| 243 exception_vector data_storage | |
| 244 exception_vector instruction_storage | |
| 245 exception_vector external | |
| 246 exception_vector alignment | |
| 247 exception_vector program | |
| 248 exception_vector floatingpoint_unavailable | |
| 249 exception_vector decrementer | |
| 250 exception_vector reserved_00a00 | |
| 251 exception_vector reserved_00b00 | |
| 252 exception_vector system_call | |
| 253 exception_vector trace | |
| 254 exception_vector floatingpoint_assist | |
| 255 exception_vector reserved_00f00 | |
| 256 | |
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257 # Variants may define extra vectors. |
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258 hal_extra_vectors |
| 0 | 259 |
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260 rom_vectors_end: |
| 0 | 261 |
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262 #else // CYGHWR_HAL_POWERPC_NEED_VECTORS |
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263 |
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264 # When vectors are not included this is the primary entry point. |
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265 .globl __exception_reset |
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266 __exception_reset: |
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267 lwi r3,_start |
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268 mtlr r3 |
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269 blr |
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270 |
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271 #endif // CYGHWR_HAL_POWERPC_NEED_VECTORS |
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272 |
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273 |
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274 |
| 2 | 275 #=========================================================================== |
| 276 # Real startup code. We jump here from the various reset vectors to set up | |
| 277 # the world. | |
| 0 | 278 |
| 279 .text | |
| 280 .globl _start | |
| 2 | 281 _start: |
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282 # Initialize CPU to a post-reset state, ensuring the ground doesn''t |
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283 # shift under us while we try to set things up. |
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284 hal_cpu_init |
| 0 | 285 |
| 286 # Set up global offset table | |
| 287 lwi r2,_GLOBAL_OFFSET_TABLE_ | |
| 288 | |
| 289 # set up time base register to zero | |
| 290 xor r3,r3,r3 | |
| 2 | 291 mtspr TBL_W,r3 |
| 0 | 292 xor r4,r4,r4 |
| 2 | 293 mtspr TBU_W,r4 |
| 294 | |
| 295 # Call platform specific hardware initialization | |
| 296 # This may include memory controller initialization. It is not | |
| 297 # safe to access RAM until after this point. | |
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298 bl hal_hardware_init # this is platform dependent |
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299 .globl _hal_hardware_init_done |
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300 _hal_hardware_init_done: |
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301 |
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302 #if !defined(CYG_HAL_STARTUP_ROM) && defined(CYGSEM_HAL_POWERPC_COPY_VECTORS) |
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303 lwi r3,rom_vectors-4 |
| 1431 | 304 lwi r4,((CYGHWR_HAL_POWERPC_VECTOR_BASE)-4) |
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305 lwi r5,rom_vectors_end-4 |
| 2438 | 306 sub r5,r5,r3 # compute number of words to copy |
| 307 srwi r5,r5,2 | |
| 308 mtctr r5 | |
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309 0: lwzu r0,4(r3) |
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310 stwu r0,4(r4) |
| 2438 | 311 bdnz 0b |
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312 #endif |
| 0 | 313 |
| 314 # set up stack | |
| 315 lwi sp,__interrupt_stack | |
| 2 | 316 mtspr SPRG0,sp # save in sprg0 for later use |
| 0 | 317 |
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318 # Set up exception handlers and VSR table, taking care not to |
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319 # step on any ROM monitor''s toes. |
| 473 | 320 hal_mon_init |
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321 |
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322 #if defined(CYG_HAL_STARTUP_ROM) |
| 0 | 323 # Copy data from ROM to ram |
| 324 lwi r3,__rom_data_start # r3 = rom start | |
| 325 lwi r4,__ram_data_start # r4 = ram start | |
| 326 lwi r5,__ram_data_end # r5 = ram end | |
| 327 | |
| 328 cmplw r4,r5 # skip if no data | |
| 329 beq 2f | |
| 2438 | 330 sub r5,r5,r4 # compute number of words to copy |
| 331 srwi r5,r5,2 | |
| 332 mtctr r5 | |
| 333 subi r3,r3,4 | |
| 334 subi r4,r4,4 | |
| 335 1: lwzu r0,4(r3) # get word from ROM | |
| 336 stwu r0,4(r4) # store in RAM | |
| 337 bdnz 1b | |
| 0 | 338 2: |
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339 #endif |
| 2 | 340 |
| 0 | 341 # clear BSS |
| 342 lwi r3,__bss_start # r3 = start | |
| 2 | 343 lwi r4,__bss_end # r4 = end |
| 0 | 344 li r0,0 # r0 = 0 |
| 345 cmplw r3,r4 # skip if no bss | |
| 346 beq 2f | |
| 2438 | 347 sub r4,r4,r3 # compute number of words to clear |
| 348 srwi r4,r4,2 | |
| 349 mtctr r4 | |
| 350 subi r3,r3,4 | |
| 0 | 351 |
| 2438 | 352 1: stwu r0,4(r3) # store zero & increment pointer |
| 353 bdnz 1b | |
| 0 | 354 2: |
| 355 | |
| 2 | 356 # clear SBSS |
| 357 lwi r3,__sbss_start # r3 = start | |
| 358 lwi r4,__sbss_end # r4 = end | |
| 359 cmplw r3,r4 # skip if no sbss | |
| 360 beq 2f | |
| 2438 | 361 sub r4,r4,r3 # compute number of words to clear |
| 362 srwi r4,r4,2 | |
| 363 mtctr r4 | |
| 364 subi r3,r3,4 | |
| 2 | 365 |
| 2438 | 366 1: stwu r0,4(r3) # store zero & increment pointer |
| 367 bdnz 1b | |
| 2 | 368 2: |
| 369 | |
| 370 # It is now safe to call C functions which may rely on initialized | |
| 371 # data. | |
| 372 | |
| 373 # Set up stack for calls to C code. | |
| 0 | 374 subi sp,sp,12 # make space on stack |
| 375 li r0,0 | |
| 376 stw r0,0(sp) # clear back chain | |
| 377 stw r0,8(sp) # zero return pc | |
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378 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 2 | 379 |
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380 # Variant HALs may need to do something special before we continue |
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381 bl hal_variant_init |
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382 |
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383 # Platform initialization |
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384 bl hal_platform_init |
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385 |
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386 # MMU and cache are controlled by the same option since caching |
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387 # on the PPC [typically] does not make sense without the MMU to mark |
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388 # regions which should not be cached. |
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389 #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU |
| 2 | 390 # Initialize MMU. |
| 391 bl hal_MMU_init | |
| 392 | |
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393 # Enable MMU (if desired) so we can safely enable caches. |
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394 lwi r3,CYG_MSR # interrupts enabled later |
| 2 | 395 sync |
| 396 mtmsr r3 | |
| 397 sync | |
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398 |
| 2 | 399 # Enable caches |
| 400 bl hal_enable_caches | |
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401 #endif // CYGHWR_HAL_POWERPC_ENABLE_MMU |
| 0 | 402 |
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403 # set up platform specific interrupt environment |
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404 bl hal_IRQ_init |
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405 |
| 2 | 406 # call c++ constructors |
| 407 bl cyg_hal_invoke_constructors | |
| 0 | 408 |
| 2 | 409 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
| 410 bl initialize_stub | |
| 0 | 411 #endif |
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412 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ |
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413 || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) |
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414 .extern hal_ctrlc_isr_init |
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415 bl hal_ctrlc_isr_init |
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416 #endif |
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417 |
| 0 | 418 bl cyg_start # call cyg_start |
| 419 9: | |
| 420 b 9b # if we return, loop | |
| 421 | |
| 2 | 422 #--------------------------------------------------------------------------- |
| 0 | 423 # This code handles the common part of all exception handlers. |
| 424 # It saves the machine state onto the stack and then calls | |
| 425 # a "C" routine to do the rest of the work. This work may result | |
| 426 # in thread switches, and changes to the saved state. When we return | |
| 427 # here the saved state is restored and execution is continued. | |
| 428 | |
| 429 .text | |
| 430 | |
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431 .globl cyg_hal_default_exception_vsr |
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432 cyg_hal_default_exception_vsr: |
| 0 | 433 |
| 434 # We come here with all register containing their | |
| 435 # pre-exception values except: | |
| 436 # R3 = ls 16 bits of vector address | |
| 437 # R4 = saved CR | |
| 438 # R5 = saved LR | |
| 439 # LR = VSR address | |
| 440 # SPRG1 = old R3 | |
| 441 # SPRG2 = old R4 | |
| 442 # SPRG3 = old R5 | |
| 443 # SRR0 = old PC | |
| 2 | 444 # SRR1 = old MSR and the exception cause (the POW state is lost!) |
| 0 | 445 |
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446 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT |
| 0 | 447 # leave space for registers and |
| 448 # a safety margin | |
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449 #ifdef CYGPKG_HAL_POWERPC_PPC40x |
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450 // The caches on this processor are always enabled when the MMU is on |
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451 // (and disabled when off). Thus we need to be careful about cache |
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452 // polution and staleness when changing the MMU state. |
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453 // At this point, the MMU is off due to the exception. We need to |
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454 // flush the part of the cache which may be touched before the MMU |
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455 // is reenabled so that memory will be consistent when that happens. |
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456 // Of course, this is complicated by the fact that there are no "free" |
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457 // registers at this point in the code. |
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458 dcbf 0,sp // Flushes first line |
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459 stw r3,0(sp) // This is now safe |
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460 li r3,CYGARC_PPCREG_VECTOR // Flush lines which will be changed |
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461 dcbf r3,sp |
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462 li r3,CYGARC_PPCREG_CR |
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463 dcbf r3,sp |
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464 li r3,CYGARC_PPCREG_LR |
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465 dcbf r3,sp |
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466 lwz r3,0(sp) // Restore register |
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467 #endif |
| 0 | 468 |
| 469 # First, save away some registers | |
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470 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector |
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471 stw r4,CYGARC_PPCREG_CR(sp) # stash CR |
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472 stw r5,CYGARC_PPCREG_LR(sp) # stash LR |
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473 |
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474 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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475 # Mark this fram as an Exception frame |
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476 lwi r3,0xDDDDDDE0 |
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477 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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478 lwi r3,0xDDDDDDE1 |
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479 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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480 #endif |
| 2 | 481 |
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482 # Enable MMU & interrupt/FPU environment (as configured) |
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483 lwi r3,CYG_MSR |
| 2 | 484 sync |
| 485 mtmsr r3 | |
| 486 sync | |
| 487 | |
| 488 mfspr r3,SPRG1 # save original R3 | |
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489 stw r3,CYGARC_PPCREG_REGS+3*4(sp) |
| 2 | 490 mfspr r4,SPRG2 # save original R4 |
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491 stw r4,CYGARC_PPCREG_REGS+4*4(sp) |
| 2 | 492 mfspr r5,SPRG3 # save original R5 |
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493 stw r5,CYGARC_PPCREG_REGS+5*4(sp) |
| 0 | 494 |
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495 stw r0,CYGARC_PPCREG_REGS+0*4(sp) # save R0 |
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496 stw r2,CYGARC_PPCREG_REGS+2*4(sp) # save R2 |
| 0 | 497 |
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498 mr r3,sp # recreate original SP |
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499 addi r3,r3,CYGARC_PPC_EXCEPTION_DECREMENT |
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500 stw r3,CYGARC_PPCREG_REGS+1*4(sp) # and save it in state |
| 0 | 501 |
| 2 | 502 # Save registers r6..r12/r31 |
| 0 | 503 .set _reg,6 |
| 504 .rept MAX_SAVE_REG+1-6 | |
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505 stw _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 506 .set _reg,_reg+1 |
| 507 .endr | |
| 508 | |
| 2 | 509 # Save registers used in vsr (r14+r15) |
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510 stw r14,(CYGARC_PPCREG_REGS+14*4)(sp) |
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511 stw r15,(CYGARC_PPCREG_REGS+15*4)(sp) |
| 2 | 512 |
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513 # get remaining family CPU registers |
| 0 | 514 mfxer r3 |
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515 mfctr r4 |
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516 mfsrr0 r5 |
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517 mfsrr1 r6 |
| 0 | 518 # and store them |
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519 stw r3,CYGARC_PPCREG_XER(sp) |
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520 stw r4,CYGARC_PPCREG_CTR(sp) |
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521 stw r5,CYGARC_PPCREG_PC(sp) |
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522 stw r6,CYGARC_PPCREG_MSR(sp) |
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523 |
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524 # Save variant registers |
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525 hal_variant_save sp |
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526 |
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527 # Save FPU registers |
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528 hal_fpu_save sp |
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529 |
| 0 | 530 # The entire CPU state is now stashed on the stack, |
| 531 # call into C to do something with it. | |
| 532 | |
| 533 mr r3,sp # R3 = register dump | |
| 534 | |
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535 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 536 |
| 537 li r0,0 # R0 = 0 | |
| 538 stw r0,0(sp) # backchain = 0 | |
| 539 stw r0,8(sp) # return pc = 0 | |
| 540 | |
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541 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 542 # where C code can save LR |
| 543 | |
| 544 lwi r5,restore_state # get return link | |
| 545 mtlr r5 # to link register | |
| 546 | |
| 2 | 547 .extern cyg_hal_exception_handler |
| 548 b cyg_hal_exception_handler # call C code, r3 = registers | |
| 0 | 549 |
| 550 # When the call returns it will go to restore_state below. | |
| 551 | |
| 552 | |
| 2 | 553 ##-------------------------------------------------------------------------- |
| 554 ## The following macros are defined depending on whether the Interrupt | |
| 555 ## system is using isr tables or chaining, and depending on the interrupt | |
| 556 ## controller in the system. | |
| 557 | |
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558 #ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED |
| 2 | 559 |
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560 ## This is the simple version. No interrupt controller, CYGARC_PPCREG_VECTOR |
| 2 | 561 ## is updated with the decoded interrupt vector. Isr tables/chaining |
| 562 ## use same interrupt decoder. | |
| 563 ## Bit 21 biffers between decrementer (0) and external (1). | |
| 564 | |
| 565 # decode the interrupt | |
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566 .macro hal_intc_decode dreg,state |
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567 lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number, |
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568 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update |
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569 stw \dreg,CYGARC_PPCREG_VECTOR(\state) # vector in state frame. |
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570 slwi \dreg,\dreg,2 # convert to word offset. |
| 2 | 571 .endm |
| 572 | |
|
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573 #endif // CYGPKG_HAL_POWERPC_INTC_DEFINED |
| 2 | 574 |
| 575 #--------------------------------------------------------------------------- | |
| 0 | 576 # Common interrupt handling code. |
| 577 | |
|
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578 .globl cyg_hal_default_interrupt_vsr |
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579 cyg_hal_default_interrupt_vsr: |
| 0 | 580 |
| 581 # We come here with all register containing their | |
| 582 # pre-exception values except: | |
| 583 # R3 = ls 16 bits of vector address | |
| 584 # R4 = saved CR | |
| 585 # R5 = saved LR | |
| 586 # LR = VSR address | |
| 587 # SPRG1 = old R3 | |
| 588 # SPRG2 = old R4 | |
| 589 # SPRG3 = old R5 | |
| 590 # SRR0 = old PC | |
| 591 # SRR1 = old MSR | |
| 592 | |
| 593 | |
|
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594 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT |
| 0 | 595 # leave space for registers and |
| 596 # a safety margin | |
|
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597 #ifdef CYGPKG_HAL_POWERPC_PPC40x |
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598 // The caches on this processor are always enabled when the MMU is on |
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599 // (and disabled when off). Thus we need to be careful about cache |
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600 // polution and staleness when changing the MMU state. |
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601 // At this point, the MMU is off due to the exception. We need to |
|
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602 // flush the part of the cache which may be touched before the MMU |
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603 // is reenabled so that memory will be consistent when that happens. |
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604 // Of course, this is complicated by the fact that there are no "free" |
|
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605 // registers at this point in the code. |
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606 dcbf 0,sp // Flushes first line |
|
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607 stw r3,0(sp) // This is now safe |
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608 li r3,CYGARC_PPCREG_VECTOR // Flush lines which will be changed |
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609 dcbf r3,sp |
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610 li r3,CYGARC_PPCREG_CR |
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611 dcbf r3,sp |
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612 li r3,CYGARC_PPCREG_LR |
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613 dcbf r3,sp |
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614 lwz r3,0(sp) // Restore register |
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615 #endif |
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616 |
|
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617 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector |
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618 stw r4,CYGARC_PPCREG_CR(sp) # stash CR |
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619 stw r5,CYGARC_PPCREG_LR(sp) # stash LR |
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620 |
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621 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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622 # Mark this fram as an 1nterrupt frame |
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623 lwi r3,0xDDDDDD10 |
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624 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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625 lwi r3,0xDDDDDD11 |
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626 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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627 #endif |
| 0 | 628 |
|
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629 # Enable MMU & interrupt/FPU environment as configured |
|
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630 lwi r3,CYG_MSR |
| 2 | 631 sync |
| 632 mtmsr r3 | |
| 633 sync | |
| 634 | |
| 635 mfspr r3,SPRG1 # save original R3 | |
|
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636 stw r3,CYGARC_PPCREG_REGS+3*4(sp) |
| 2 | 637 mfspr r4,SPRG2 # save original R4 |
|
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638 stw r4,CYGARC_PPCREG_REGS+4*4(sp) |
| 2 | 639 mfspr r5,SPRG3 # save original R5 |
|
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640 stw r5,CYGARC_PPCREG_REGS+5*4(sp) |
| 0 | 641 |
|
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642 stw r0,CYGARC_PPCREG_REGS+0*4(sp) # save R0 |
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643 stw r2,CYGARC_PPCREG_REGS+2*4(sp) # save R2 |
| 0 | 644 |
|
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645 mr r3,sp # recreate original SP |
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646 addi r3,r3,CYGARC_PPC_EXCEPTION_DECREMENT |
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647 stw r3,CYGARC_PPCREG_REGS+1*4(sp) # and save it in state |
| 0 | 648 |
| 2 | 649 # Save registers r6..r12/r31 |
| 0 | 650 .set _reg,6 |
| 651 .rept MAX_SAVE_REG+1-6 | |
|
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652 stw _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 653 .set _reg,_reg+1 |
| 654 .endr | |
| 655 | |
| 2 | 656 # Save registers used in vsr (r14+r15) |
|
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657 stw r14,CYGARC_PPCREG_REGS+14*4(sp) |
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658 stw r15,CYGARC_PPCREG_REGS+15*4(sp) |
| 2 | 659 |
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660 # get remaining family CPU registers |
| 0 | 661 mfxer r3 |
|
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662 mfctr r4 |
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663 mfsrr0 r5 |
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664 mfsrr1 r6 |
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665 |
| 0 | 666 # and store them |
|
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667 stw r3,CYGARC_PPCREG_XER(sp) |
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668 stw r4,CYGARC_PPCREG_CTR(sp) |
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669 stw r5,CYGARC_PPCREG_PC(sp) |
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670 stw r6,CYGARC_PPCREG_MSR(sp) |
| 0 | 671 |
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672 # Save variant registers |
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673 hal_variant_save sp |
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674 |
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675 # Save FPU registers |
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676 hal_fpu_save sp |
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677 |
| 0 | 678 # The entire CPU state is now stashed on the stack, |
| 679 # increment the scheduler lock and call the ISR | |
| 680 # for this vector. | |
| 681 | |
| 682 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 2 | 683 .extern cyg_scheduler_sched_lock |
| 684 lwi r3,cyg_scheduler_sched_lock | |
| 0 | 685 lwz r4,0(r3) |
| 686 addi r4,r4,1 | |
| 687 stw r4,0(r3) | |
| 688 #endif | |
| 689 | |
| 2 | 690 mr r14,sp # r14 = register dump |
| 0 | 691 |
| 692 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 693 lwi r3,__interrupt_stack # stack top | |
| 694 lwi r4,__interrupt_stack_base # stack base | |
| 695 sub. r5,sp,r4 # sp - base | |
| 696 blt 1f # if < 0 - not on istack | |
| 697 sub. r5,r3,sp # top - sp | |
| 698 bgt 2f # if > 0 - already on istack | |
| 699 | |
| 700 1: mr sp,r3 # switch to istack | |
| 701 | |
| 2 | 702 2: stwu r14,-4(sp) # save old SP on stack |
| 0 | 703 |
| 704 #endif | |
| 705 | |
|
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706 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 707 |
| 708 li r0,0 # R0 = 0 | |
| 709 stw r0,0(sp) # backchain = 0 | |
| 710 stw r0,8(sp) # return pc = 0 | |
| 711 | |
|
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712 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 713 # where C code can save LR |
| 714 | |
| 715 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 716 | |
| 717 lwi r3,0x0301 # r3 = type = INTR,RAISE | |
|
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718 lwz r4,CYGARC_PPCREG_VECTOR(r14) # arg1 = vector address |
| 0 | 719 srwi r4,r4,8 # arg1 = vector number |
| 720 xor r5,r5,r5 # arg2 = 0 | |
| 721 bl cyg_instrument # call instrument function | |
| 722 | |
| 723 #endif | |
| 724 | |
|
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725 hal_intc_decode r15,r14 # get table index |
| 2 | 726 |
|
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727 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ |
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728 || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) |
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729 # If we are supporting Ctrl-C interrupts from GDB, we must squirrel |
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730 # away a pointer to the save interrupt state here so that we can |
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731 # plant a breakpoint at some later time. |
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732 |
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733 .extern hal_saved_interrupt_state |
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734 lwi r3,hal_saved_interrupt_state |
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735 stw r14,0(r3) |
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736 |
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737 #endif |
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738 |
| 2 | 739 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING |
| 0 | 740 |
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741 #ifdef CYGPKG_HAL_POWERPC_MPC8xx |
| 2 | 742 # The CPM controller allows nested interrupts. However, |
| 743 # it sits on the back of the SIU controller which has no | |
| 744 # HW support for this. In effect, SW masking of lower | |
| 745 # priority IRQs in the SIU would be required for this to work. | |
| 746 #endif | |
| 747 | |
| 748 #endif | |
| 749 | |
|
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750 lwz r3,CYGARC_PPCREG_VECTOR(r14) # retrieve decoded vector # |
| 0 | 751 |
| 752 lwi r6,hal_interrupt_handlers # get interrupt handler table | |
| 753 lwzx r6,r6,r15 # load routine pointer | |
| 754 | |
| 755 lwi r4,hal_interrupt_data # get interrupt data table | |
| 756 lwzx r4,r4,r15 # load data pointer | |
| 757 # R4 = data argument | |
| 423 | 758 mr r5,r14 # R5 = saved registers |
| 0 | 759 |
| 760 mtctr r6 # put isr address in ctr | |
| 761 | |
| 762 bctrl # branch to ctr reg and link | |
| 763 | |
| 764 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 765 | |
| 766 # If we are returning from the last nested interrupt, move back | |
| 767 # to the thread stack. interrupt_end() must be called on the | |
| 768 # thread stack since it potentially causes a context switch. | |
| 769 # Since we have arranged for the top of stack location to | |
| 770 # contain the sp we need to go back to here, just pop it off | |
| 771 # and put it in SP. | |
| 772 | |
| 773 | |
|
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774 lwz sp,CYGARC_PPC_STACK_FRAME_SIZE*2(sp) # sp = *sp |
| 0 | 775 |
|
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776 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 777 |
| 778 li r0,0 # R0 = 0 | |
| 779 stw r0,0(sp) # backchain = 0 | |
| 780 stw r0,8(sp) # return pc = 0 | |
| 781 | |
|
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782 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 783 # where C code can save LR |
| 784 #endif | |
| 785 | |
|
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786 # On return r3 bit 1 will indicate whether a DSR is |
| 0 | 787 # to be posted. Pass this together with a pointer to |
| 788 # the interrupt object we have just used to the | |
| 789 # interrupt tidy up routine. | |
| 790 | |
| 2 | 791 # Note that r14 and r15 are defined to be preserved across |
| 0 | 792 # calls by the calling convention, so they still contain |
| 793 # the register dump and the vector number respectively. | |
| 2 | 794 |
| 0 | 795 lwi r4,hal_interrupt_objects # get interrupt object table |
| 796 lwzx r4,r4,r15 # load object pointer | |
|
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797 mr r5,r14 # arg3 = saved register dump |
| 0 | 798 |
| 799 .extern interrupt_end | |
| 800 bl interrupt_end # call into C to finish off | |
| 801 | |
| 802 restore_state: | |
| 803 # All done, restore CPU state and continue | |
| 804 | |
|
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805 # retrieve CPU state pointer |
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806 addi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE*2 |
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807 |
|
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808 # Restore FPU registers |
|
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809 hal_fpu_load sp |
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810 |
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811 # Restore variant registers |
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812 hal_variant_load sp |
| 0 | 813 |
| 814 # get sprs we want to restore | |
|
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815 # stuff some of them into the CPU |
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816 lwz r3,CYGARC_PPCREG_XER(sp) |
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817 lwz r4,CYGARC_PPCREG_LR(sp) |
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818 lwz r5,CYGARC_PPCREG_CTR(sp) |
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819 mtxer r3 |
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820 mtlr r4 |
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821 mtctr r5 |
| 0 | 822 |
| 2 | 823 # Restore registers used in vsr (r14+r15) |
|
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824 lwz r14,CYGARC_PPCREG_REGS+14*4(r1) |
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825 lwz r15,CYGARC_PPCREG_REGS+15*4(r1) |
| 2 | 826 |
| 827 # restore registers r6..r12/r31 | |
| 0 | 828 .set _reg,6 |
| 829 .rept MAX_SAVE_REG+1-6 | |
|
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830 lwz _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 831 .set _reg,_reg+1 |
| 832 .endr | |
| 833 | |
|
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834 hal_cpu_int_disable |
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835 |
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836 # restore R0 and R2 |
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837 lwz r0,CYGARC_PPCREG_REGS+0*4(sp) |
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838 lwz r2,CYGARC_PPCREG_REGS+2*4(sp) |
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839 |
| 0 | 840 # Here all the registers are loaded except |
|
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841 # sp = HAL_SavedRegisters |
| 0 | 842 # r3 = ccr |
| 843 # r4 = srr0 = pc | |
| 844 # r5 = srr1 = msr | |
|
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845 # |
| 0 | 846 # We have to disable interrupts while srr0 and |
| 847 # srr1 are loaded, since another interrupt will | |
| 848 # destroy them. | |
| 849 | |
|
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850 lwz r3,CYGARC_PPCREG_CR(sp) |
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851 lwz r4,CYGARC_PPCREG_PC(sp) |
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852 lwz r5,CYGARC_PPCREG_MSR(sp) |
| 0 | 853 mtcr r3 # set ccr |
| 854 mtsrr0 r4 # load old pc | |
| 855 mtsrr1 r5 # load old msr | |
| 856 | |
|
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857 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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858 # Mark this frame as (almost) dead. |
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859 lwi r3,0xDDDDDDD0 |
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860 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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861 lwi r3,0xDDDDDDD1 |
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862 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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863 #endif |
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864 |
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865 lwz r3,CYGARC_PPCREG_REGS+3*4(sp) # load r3 value |
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866 lwz r4,CYGARC_PPCREG_REGS+4*4(sp) # load r4 value |
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867 lwz r5,CYGARC_PPCREG_REGS+5*4(sp) # load r5 value |
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868 lwz sp,CYGARC_PPCREG_REGS+1*4(sp) # restore sp |
| 0 | 869 |
| 870 sync # settle things down | |
| 871 isync | |
| 872 rfi # and return | |
| 873 | |
|
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874 |
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875 |
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876 ##----------------------------------------------------------------------------- |
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877 ## Execute pending DSRs on the interrupt stack with interrupts enabled. |
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878 ## Note: this can only be called from code running on a thread stack |
|
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879 |
|
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880 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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881 .extern cyg_interrupt_call_pending_DSRs |
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882 |
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883 FUNC_START(hal_interrupt_stack_call_pending_DSRs) |
|
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884 # Change to interrupt stack, save state and set up stack for |
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885 # calls to C code. |
|
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886 mr r3,sp |
|
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887 lwi r4,__interrupt_stack |
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888 subi r4,r4,24 # make space on stack |
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889 mr sp,r4 |
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890 stw r3,12(sp) # save old sp |
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891 mfmsr r3 |
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892 stw r3,16(sp) # save old MSR |
|
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893 mflr r3 |
|
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894 stw r3,20(sp) # save old LR |
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895 |
|
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896 li r0,0 |
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897 stw r0,0(sp) # clear back chain |
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898 stw r0,8(sp) # zero return pc |
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899 |
|
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900 hal_cpu_int_enable |
|
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901 |
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902 # Call into kernel which will execute DSRs |
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903 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) |
|
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904 bl cyg_interrupt_call_pending_DSRs |
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905 addi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE |
|
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906 |
|
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907 lwz r3,20(sp) # restore LR |
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908 mtlr r3 |
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909 lwz r5,12(sp) # get SP from saved state |
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910 lwz r3,16(sp) # restore interrupt setting |
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911 hal_cpu_int_merge r3 |
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912 |
|
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913 mr sp,r5 # restore stack pointer |
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914 blr # and return to caller |
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915 #endif |
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916 |
| 2 | 917 #--------------------------------------------------------------------------- |
| 0 | 918 ## Temporary interrupt stack |
| 919 | |
| 920 .section ".bss" | |
| 921 | |
| 922 .balign 16 | |
|
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923 .global cyg_interrupt_stack_base |
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924 cyg_interrupt_stack_base: |
| 0 | 925 __interrupt_stack_base: |
| 926 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 927 .byte 0 | |
| 928 .endr | |
| 929 .balign 16 | |
|
8
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
930 .global cyg_interrupt_stack |
|
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
931 cyg_interrupt_stack: |
| 0 | 932 __interrupt_stack: |
| 933 | |
| 934 .long 0,0,0,0,0,0,0,0 | |
| 935 | |
| 2 | 936 #--------------------------------------------------------------------------- |
| 0 | 937 # end of vectors.S |