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annotate packages/kernel/current/src/intr/intr.cxx @ 210:d2c90368aeef
Merge from eCos master repository on 2002-05-23-21:39:14-BST
| author | jlarmour |
|---|---|
| date | Thu, 23 May 2002 22:59:51 +0000 |
| parents | e0c0827131d1 |
| children | 13625e7b9d1f |
| rev | line source |
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| 0 | 1 //========================================================================== |
| 2 // | |
| 2 | 3 // intr/intr.cxx |
| 0 | 4 // |
| 2 | 5 // Interrupt class implementations |
| 0 | 6 // |
| 7 //========================================================================== | |
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8 //####ECOSGPLCOPYRIGHTBEGIN#### |
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9 // ------------------------------------------- |
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10 // This file is part of eCos, the Embedded Configurable Operating System. |
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
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12 // |
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13 // eCos is free software; you can redistribute it and/or modify it under |
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14 // the terms of the GNU General Public License as published by the Free |
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15 // Software Foundation; either version 2 or (at your option) any later version. |
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16 // |
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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20 // for more details. |
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21 // |
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22 // You should have received a copy of the GNU General Public License along |
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23 // with eCos; if not, write to the Free Software Foundation, Inc., |
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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25 // |
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26 // As a special exception, if other files instantiate templates or use macros |
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27 // or inline functions from this file, or you compile this file and link it |
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28 // with other works to produce a work based on this file, this file does not |
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29 // by itself cause the resulting work to be covered by the GNU General Public |
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30 // License. However the source code for this file must still be made available |
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31 // in accordance with section (3) of the GNU General Public License. |
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32 // |
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33 // This exception does not invalidate any other reasons why a work based on |
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34 // this file might be covered by the GNU General Public License. |
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35 // |
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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37 // at http://sources.redhat.com/ecos/ecos-license/ |
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38 // ------------------------------------------- |
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39 //####ECOSGPLCOPYRIGHTEND#### |
| 0 | 40 //========================================================================== |
| 41 //#####DESCRIPTIONBEGIN#### | |
| 42 // | |
| 2 | 43 // Author(s): nickg |
| 44 // Contributors: nickg | |
| 45 // Date: 1999-02-17 | |
| 46 // Purpose: Interrupt class implementation | |
| 47 // Description: This file contains the definitions of the interrupt | |
| 48 // class. | |
| 0 | 49 // |
| 50 //####DESCRIPTIONEND#### | |
| 51 // | |
| 52 //========================================================================== | |
| 53 | |
| 54 #include <pkgconf/kernel.h> | |
| 55 | |
| 56 #include <cyg/kernel/ktypes.h> // base kernel types | |
| 57 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 58 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 59 #include <cyg/kernel/instrmnt.h> // instrumentation | |
| 60 | |
| 61 #include <cyg/kernel/intr.hxx> // our header | |
| 62 | |
| 63 #include <cyg/kernel/sched.hxx> // scheduler | |
| 64 | |
| 65 #include <cyg/kernel/sched.inl> | |
| 66 | |
| 67 // ------------------------------------------------------------------------- | |
| 2 | 68 // Statics |
| 69 | |
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70 volatile cyg_int32 Cyg_Interrupt::disable_counter[CYGNUM_KERNEL_CPU_MAX]; |
| 2 | 71 |
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72 Cyg_SpinLock Cyg_Interrupt::interrupt_disable_spinlock CYG_INIT_PRIORITY( INTERRUPTS ); |
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73 |
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74 CYG_INTERRUPT_STATE Cyg_Interrupt::interrupt_disable_state[CYGNUM_KERNEL_CPU_MAX]; |
| 2 | 75 |
| 76 // ------------------------------------------------------------------------- | |
| 0 | 77 |
| 78 Cyg_Interrupt::Cyg_Interrupt( | |
| 79 cyg_vector vec, // Vector to attach to | |
| 80 cyg_priority pri, // Queue priority | |
| 81 CYG_ADDRWORD d, // Data pointer | |
| 82 cyg_ISR *ir, // Interrupt Service Routine | |
| 83 cyg_DSR *dr // Deferred Service Routine | |
| 84 ) | |
| 85 { | |
| 2 | 86 CYG_REPORT_FUNCTION(); |
| 87 CYG_REPORT_FUNCARG5("vector=%d, priority=%d, data=%08x, isr=%08x, " | |
| 88 "dsr=%08x", vec, pri, d, ir, dr); | |
| 89 | |
| 0 | 90 vector = vec; |
| 91 priority = pri; | |
| 92 isr = ir; | |
| 93 dsr = dr; | |
| 94 data = d; | |
| 95 | |
| 96 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
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97 |
| 0 | 98 dsr_count = 0; |
| 99 next_dsr = NULL; | |
| 100 | |
| 101 #endif | |
| 102 | |
| 103 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 104 | |
| 105 next = NULL; | |
| 106 | |
| 107 #endif | |
| 2 | 108 |
| 109 CYG_REPORT_RETURN(); | |
| 0 | 110 |
| 111 }; | |
| 112 | |
| 113 // ------------------------------------------------------------------------- | |
| 114 | |
| 115 Cyg_Interrupt::~Cyg_Interrupt() | |
| 116 { | |
| 2 | 117 CYG_REPORT_FUNCTION(); |
| 0 | 118 detach(); |
| 2 | 119 CYG_REPORT_RETURN(); |
| 0 | 120 }; |
| 121 | |
| 122 // ------------------------------------------------------------------------- | |
| 123 // DSR handling statics: | |
| 124 | |
| 125 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 126 | |
| 2 | 127 Cyg_Interrupt * |
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128 Cyg_Interrupt::dsr_table[CYGNUM_KERNEL_CPU_MAX][CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]; |
| 0 | 129 |
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130 cyg_ucount32 Cyg_Interrupt::dsr_table_head[CYGNUM_KERNEL_CPU_MAX]; |
| 0 | 131 |
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132 volatile cyg_ucount32 Cyg_Interrupt::dsr_table_tail[CYGNUM_KERNEL_CPU_MAX]; |
| 0 | 133 |
| 134 #endif | |
| 135 | |
| 136 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 137 | |
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138 Cyg_Interrupt* volatile Cyg_Interrupt::dsr_list[CYGNUM_KERNEL_CPU_MAX]; |
| 0 | 139 |
| 140 #endif | |
| 141 | |
| 142 // ------------------------------------------------------------------------- | |
| 143 // Call any pending DSRs | |
| 144 | |
| 2 | 145 void |
| 146 Cyg_Interrupt::call_pending_DSRs_inner(void) | |
| 0 | 147 { |
| 148 // CYG_REPORT_FUNCTION(); | |
| 149 | |
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150 HAL_SMP_CPU_TYPE cpu = CYG_KERNEL_CPU_THIS(); |
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151 |
| 0 | 152 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE |
| 153 | |
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154 while( dsr_table_head[cpu] != dsr_table_tail[cpu] ) |
| 0 | 155 { |
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156 Cyg_Interrupt *intr = dsr_table[cpu][dsr_table_head[cpu]]; |
| 0 | 157 |
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158 dsr_table_head[cpu]++; |
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159 if( dsr_table_head[cpu] >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) |
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160 dsr_table_head[cpu] = 0; |
| 0 | 161 |
| 162 CYG_INSTRUMENT_INTR(CALL_DSR, intr->vector, 0); | |
| 163 | |
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164 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
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165 |
| 0 | 166 intr->dsr( intr->vector, 1, (CYG_ADDRWORD)intr->data ); |
| 167 } | |
| 168 | |
| 169 #endif | |
| 170 | |
| 171 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 172 | |
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173 while( dsr_list[cpu] != NULL ) |
| 0 | 174 { |
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175 Cyg_Interrupt* intr; |
| 0 | 176 cyg_uint32 old_intr; |
| 177 cyg_count32 count; | |
| 178 | |
| 179 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 180 | |
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181 intr = dsr_list[cpu]; |
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182 dsr_list[cpu] = intr->next_dsr; |
| 0 | 183 count = intr->dsr_count; |
| 184 intr->dsr_count = 0; | |
| 185 | |
| 186 HAL_RESTORE_INTERRUPTS(old_intr); | |
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187 |
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188 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
| 0 | 189 |
| 190 intr->dsr( intr->vector, count, (CYG_ADDRWORD)intr->data ); | |
| 191 | |
| 192 } | |
| 193 | |
| 194 #endif | |
| 195 | |
| 196 }; | |
| 197 | |
| 2 | 198 externC void |
| 199 cyg_interrupt_call_pending_DSRs(void) | |
| 200 { | |
| 201 Cyg_Interrupt::call_pending_DSRs_inner(); | |
| 202 } | |
| 203 | |
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204 // |
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205 // Use HAL supported function to run through the DSRs, but executing using |
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206 // the separate interrupt stack if available. This function calls back |
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207 // into this module via 'cyg_interrupt_call_pending_DSRs' above, to keep |
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208 // the whole process as general as possible. |
| 2 | 209 |
| 210 void | |
| 211 Cyg_Interrupt::call_pending_DSRs(void) | |
| 212 { | |
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213 CYG_ASSERT( Cyg_Scheduler::get_sched_lock() == 1, |
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214 "DSRs being called with sched_lock not equal to 1"); |
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215 HAL_INTERRUPT_STACK_CALL_PENDING_DSRS(); |
| 2 | 216 } |
| 217 | |
| 218 | |
| 0 | 219 // ------------------------------------------------------------------------- |
| 220 | |
| 2 | 221 void |
| 222 Cyg_Interrupt::post_dsr(void) | |
| 0 | 223 { |
| 224 // CYG_REPORT_FUNCTION(); | |
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225 HAL_SMP_CPU_TYPE cpu = CYG_KERNEL_CPU_THIS(); |
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226 |
| 0 | 227 CYG_INSTRUMENT_INTR(POST_DSR, vector, 0); |
| 228 | |
| 229 cyg_uint32 old_intr; | |
| 230 | |
| 231 // We need to disable interrupts during this part to | |
| 232 // guard against nested interrupts. | |
| 233 | |
| 234 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 235 | |
| 236 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 237 | |
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238 dsr_table[cpu][dsr_table_tail[cpu]++] = this; |
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239 if( dsr_table_tail[cpu] >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) |
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240 dsr_table_tail[cpu] = 0; |
| 0 | 241 |
| 242 #endif | |
| 243 | |
| 244 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 245 | |
| 246 // Only add the interrupt to the dsr list if this is | |
| 247 // the first DSR call. | |
| 248 // At present DSRs are pushed onto the list and will be | |
| 249 // called in reverse order. We do not define the order | |
| 250 // in which DSRs are called, so this is acceptable. | |
| 251 | |
| 252 if( dsr_count++ == 0 ) | |
| 253 { | |
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254 next_dsr = dsr_list[cpu]; |
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255 dsr_list[cpu] = this; |
| 0 | 256 } |
| 257 | |
| 258 #endif | |
| 259 | |
| 260 HAL_RESTORE_INTERRUPTS(old_intr); | |
| 261 }; | |
| 262 | |
| 263 // ------------------------------------------------------------------------- | |
| 2 | 264 // A C callable interface to Cyg_Interrupt::post_dsr() that can be used from |
| 265 // the HAL. | |
| 0 | 266 |
| 2 | 267 externC void |
| 268 cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj ) | |
| 269 { | |
| 270 Cyg_Interrupt* intr = (Cyg_Interrupt*) intr_obj; | |
| 271 intr->post_dsr (); | |
| 272 } | |
| 273 | |
| 274 // ------------------------------------------------------------------------- | |
| 275 | |
| 276 // FIXME: should have better name - Jifl | |
| 277 externC void | |
| 278 interrupt_end( | |
| 0 | 279 cyg_uint32 isr_ret, |
| 280 Cyg_Interrupt *intr, | |
| 281 HAL_SavedRegisters *regs | |
| 282 ) | |
| 283 { | |
| 284 // CYG_REPORT_FUNCTION(); | |
| 285 | |
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286 #ifdef CYGPKG_KERNEL_SMP_SUPPORT |
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287 Cyg_Scheduler::lock(); |
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288 #endif |
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289 |
| 2 | 290 // Sometimes we have a NULL intr object pointer. |
| 291 cyg_vector vector = (intr!=NULL)?intr->vector:0; | |
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292 |
| 2 | 293 CYG_INSTRUMENT_INTR(END, vector, isr_ret); |
| 294 | |
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295 CYG_UNUSED_PARAM( cyg_vector, vector ); // prevent compiler warning |
| 2 | 296 |
| 0 | 297 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
| 298 | |
| 299 // Only do this if we are in a non-chained configuration. | |
| 300 // If we are chained, then chain_isr below will do the DSR | |
| 301 // posting. | |
| 302 | |
| 2 | 303 if( isr_ret & Cyg_Interrupt::CALL_DSR && intr != NULL ) intr->post_dsr(); |
| 0 | 304 |
| 305 #endif | |
| 306 | |
| 307 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 308 | |
| 309 // If we have GDB support enabled, and there is the possibility | |
| 310 // that this thread will be context switched as a result of this | |
| 311 // interrupt, then save the pointer to the saved thread context in | |
| 312 // the thread object so that GDB can get a meaningful context to | |
| 313 // look at. | |
| 314 | |
| 315 Cyg_Scheduler::get_current_thread()->set_saved_context(regs); | |
| 316 | |
| 317 #endif | |
| 318 | |
| 319 // Now unlock the scheduler, which may also call DSRs | |
| 320 // and cause a thread switch to happen. | |
| 321 | |
| 322 Cyg_Scheduler::unlock(); | |
| 323 | |
| 324 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 325 | |
| 326 Cyg_Scheduler::get_current_thread()->set_saved_context(0); | |
| 327 | |
| 328 #endif | |
| 329 | |
| 2 | 330 CYG_INSTRUMENT_INTR(RESTORE, vector, 0); |
| 0 | 331 } |
| 332 | |
| 333 // ------------------------------------------------------------------------- | |
| 334 // Interrupt chaining statics. | |
| 335 | |
| 336 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 337 | |
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338 Cyg_Interrupt *Cyg_Interrupt::chain_list[CYGNUM_HAL_ISR_TABLE_SIZE]; |
| 0 | 339 |
| 340 #endif | |
| 341 | |
| 342 // ------------------------------------------------------------------------- | |
| 343 // Chaining ISR inserted in HAL vector | |
| 344 | |
| 345 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 346 | |
| 2 | 347 cyg_uint32 |
| 348 Cyg_Interrupt::chain_isr(cyg_vector vector, CYG_ADDRWORD data) | |
| 0 | 349 { |
| 350 Cyg_Interrupt *p = *(Cyg_Interrupt **)data; | |
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351 register cyg_uint32 isr_ret = 0; |
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352 register cyg_uint32 isr_chain_ret = 0; |
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353 |
| 0 | 354 CYG_INSTRUMENT_INTR(CHAIN_ISR, vector, 0); |
| 355 | |
| 356 while( p != NULL ) | |
| 357 { | |
| 358 if( p->vector == vector ) | |
| 359 { | |
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360 isr_ret = p->isr(vector, p->data); |
| 0 | 361 |
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362 isr_chain_ret |= isr_ret; |
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363 |
| 2 | 364 if( isr_ret & Cyg_Interrupt::CALL_DSR ) p->post_dsr(); |
| 0 | 365 |
| 2 | 366 if( isr_ret & Cyg_Interrupt::HANDLED ) break; |
| 0 | 367 } |
| 368 | |
| 369 p = p->next; | |
| 370 } | |
| 371 | |
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372 #ifdef HAL_DEFAULT_ISR |
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373 if( (isr_chain_ret & (Cyg_Interrupt::HANDLED|Cyg_Interrupt::CALL_DSR)) == 0 ) |
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374 { |
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375 // If we finished the loop for some reason other than that an |
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376 // ISR has handled the interrupt, call any default ISR to either |
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377 // report the spurious interrupt, or do some other HAL level processing |
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378 // such as GDB interrupt detection etc. |
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379 |
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380 HAL_DEFAULT_ISR( vector, 0 ); |
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381 } |
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382 #endif |
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383 |
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384 return isr_ret & ~Cyg_Interrupt::CALL_DSR; |
| 0 | 385 } |
| 386 | |
| 387 #endif | |
| 388 | |
| 389 // ------------------------------------------------------------------------- | |
| 390 // Attach an ISR to an interrupt vector. | |
| 391 | |
| 2 | 392 void |
| 393 Cyg_Interrupt::attach(void) | |
| 0 | 394 { |
| 395 CYG_REPORT_FUNCTION(); | |
| 396 | |
| 2 | 397 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 398 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 399 |
| 400 CYG_INSTRUMENT_INTR(ATTACH, vector, 0); | |
| 401 | |
| 402 HAL_INTERRUPT_SET_LEVEL( vector, priority ); | |
| 403 | |
| 404 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 405 | |
| 406 CYG_ASSERT( next == NULL , "Cyg_Interrupt already on a list"); | |
| 407 | |
| 408 cyg_uint32 index; | |
| 409 | |
| 410 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 411 | |
| 412 if( chain_list[index] == NULL ) | |
| 413 { | |
| 2 | 414 int in_use; |
| 0 | 415 // First Interrupt on this chain, just assign it and register |
| 416 // the chain_isr with the HAL. | |
| 417 | |
| 418 chain_list[index] = this; | |
| 419 | |
| 2 | 420 HAL_INTERRUPT_IN_USE( vector, in_use ); |
| 421 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 0 | 422 HAL_INTERRUPT_ATTACH( vector, chain_isr, &chain_list[index], NULL ); |
| 423 } | |
| 424 else | |
| 425 { | |
| 426 // There are already interrupts chained, add this one into the | |
| 427 // chain in priority order. | |
| 428 | |
| 429 Cyg_Interrupt **p = &chain_list[index]; | |
| 430 | |
| 431 while( *p != NULL ) | |
| 432 { | |
| 433 Cyg_Interrupt *n = *p; | |
| 434 | |
| 435 if( n->priority < priority ) break; | |
| 436 | |
| 437 p = &n->next; | |
| 438 } | |
| 439 next = *p; | |
| 440 *p = this; | |
| 441 } | |
| 442 | |
| 443 #else | |
| 444 | |
| 2 | 445 { |
| 446 int in_use; | |
| 447 | |
| 448 | |
| 449 HAL_INTERRUPT_IN_USE( vector, in_use ); | |
| 450 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 451 | |
| 452 HAL_INTERRUPT_ATTACH( vector, isr, data, this ); | |
| 453 } | |
| 0 | 454 |
| 455 #endif | |
| 2 | 456 CYG_REPORT_RETURN(); |
| 0 | 457 } |
| 458 | |
| 459 // ------------------------------------------------------------------------- | |
| 460 // Detach the ISR from the vector | |
| 461 | |
| 2 | 462 void |
| 463 Cyg_Interrupt::detach(void) | |
| 0 | 464 { |
| 465 CYG_REPORT_FUNCTION(); | |
| 466 | |
| 2 | 467 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 468 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 469 |
| 470 CYG_INSTRUMENT_INTR(DETACH, vector, 0); | |
| 471 | |
| 472 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 473 | |
| 474 // Remove the interrupt object from the vector chain. | |
| 475 | |
| 2 | 476 cyg_uint32 index; |
| 477 | |
| 478 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 479 | |
| 480 Cyg_Interrupt **p = &chain_list[index]; | |
| 0 | 481 |
| 482 while( *p != NULL ) | |
| 483 { | |
| 484 Cyg_Interrupt *n = *p; | |
| 485 | |
| 486 if( n == this ) | |
| 487 { | |
| 488 *p = next; | |
| 489 break; | |
| 490 } | |
| 491 | |
| 492 p = &n->next; | |
| 493 } | |
| 494 | |
| 495 // If this was the last one, detach the vector. | |
| 496 | |
| 2 | 497 if( chain_list[index] == NULL ) |
| 0 | 498 HAL_INTERRUPT_DETACH( vector, chain_isr ); |
| 499 | |
| 500 #else | |
| 501 | |
| 502 HAL_INTERRUPT_DETACH( vector, isr ); | |
| 503 | |
| 504 #endif | |
| 2 | 505 |
| 506 CYG_REPORT_RETURN(); | |
| 0 | 507 |
| 508 } | |
| 509 | |
| 510 // ------------------------------------------------------------------------- | |
| 511 // Get the current service routine | |
| 512 | |
| 2 | 513 void |
| 514 Cyg_Interrupt::get_vsr(cyg_vector vector, cyg_VSR **vsr) | |
| 0 | 515 { |
| 516 CYG_REPORT_FUNCTION(); | |
| 2 | 517 CYG_REPORT_FUNCARG2("vector = %d, mem to put VSR in is at %08x", vector, |
| 518 vsr); | |
| 0 | 519 |
| 2 | 520 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 521 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 522 |
| 523 HAL_VSR_GET( vector, vsr ); | |
| 2 | 524 |
| 525 CYG_REPORT_RETURN(); | |
| 0 | 526 } |
| 527 | |
| 528 // ------------------------------------------------------------------------- | |
| 529 // Install a vector service routine | |
| 530 | |
| 2 | 531 void |
| 532 Cyg_Interrupt::set_vsr(cyg_vector vector, cyg_VSR *vsr, cyg_VSR **old) | |
| 0 | 533 { |
| 534 CYG_REPORT_FUNCTION(); | |
| 535 | |
| 2 | 536 CYG_REPORT_FUNCARG3( "vector = %d, new vsr is at %08x, mem to put " |
| 537 "old VSR in is at %08x", vector, vsr, old); | |
| 538 | |
| 0 | 539 CYG_INSTRUMENT_INTR(SET_VSR, vector, vsr); |
| 540 | |
| 2 | 541 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 542 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 543 |
| 544 CYG_INTERRUPT_STATE old_ints; | |
| 545 | |
| 546 HAL_DISABLE_INTERRUPTS(old_ints); | |
| 547 | |
| 548 HAL_VSR_SET( vector, vsr, old ); | |
| 549 | |
| 550 HAL_RESTORE_INTERRUPTS(old_ints); | |
| 2 | 551 |
| 552 CYG_REPORT_RETURN(); | |
| 0 | 553 } |
| 554 | |
| 555 // ------------------------------------------------------------------------- | |
| 556 // Disable interrupts at the CPU | |
| 557 | |
| 558 | |
| 2 | 559 void |
| 560 Cyg_Interrupt::disable_interrupts(void) | |
| 0 | 561 { |
| 562 CYG_REPORT_FUNCTION(); | |
| 563 | |
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564 CYG_INSTRUMENT_INTR(DISABLE, disable_counter[CYG_KERNEL_CPU_THIS()]+1, 0); |
| 0 | 565 |
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566 HAL_SMP_CPU_TYPE cpu_this = CYG_KERNEL_CPU_THIS(); |
| 0 | 567 |
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568 // If the disable_counter is zero, disable interrupts and claim the spinlock. |
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569 |
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570 if( 0 == disable_counter[cpu_this] ) |
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571 { |
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572 // Claim the spinlock and disable interrupts. We save the original interrupt |
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573 // enable state to restore later. |
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574 interrupt_disable_spinlock.spin_intsave(&interrupt_disable_state[cpu_this]); |
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575 } |
| 0 | 576 |
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577 // Now increment our disable counter. |
| 2 | 578 |
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579 disable_counter[cpu_this]++; |
| 2 | 580 |
| 581 CYG_REPORT_RETURN(); | |
| 0 | 582 } |
| 583 | |
| 584 | |
| 585 // ------------------------------------------------------------------------- | |
| 586 // Re-enable CPU interrupts | |
| 587 | |
| 2 | 588 void |
| 589 Cyg_Interrupt::enable_interrupts(void) | |
| 0 | 590 { |
| 591 CYG_REPORT_FUNCTION(); | |
| 592 | |
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593 CYG_INSTRUMENT_INTR(ENABLE, disable_counter[CYG_KERNEL_CPU_THIS()], 0); |
| 2 | 594 |
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595 HAL_SMP_CPU_TYPE cpu_this = CYG_KERNEL_CPU_THIS(); |
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596 |
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597 CYG_ASSERT( disable_counter[cpu_this] > 0 , "Disable counter not greater than zero"); |
| 2 | 598 |
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599 // If the disable counter goes to zero, then release the spinlock and restore |
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600 // the previous interrupt state. |
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601 |
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602 if( --disable_counter[cpu_this] == 0 ) |
| 2 | 603 { |
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604 interrupt_disable_spinlock.clear_intsave(interrupt_disable_state[cpu_this]); |
| 2 | 605 } |
| 606 | |
| 607 CYG_REPORT_RETURN(); | |
| 0 | 608 } |
| 609 | |
| 610 // ------------------------------------------------------------------------- | |
| 611 // Mask a specific interrupt in a PIC | |
| 612 | |
| 2 | 613 void |
| 614 Cyg_Interrupt::mask_interrupt(cyg_vector vector) | |
| 0 | 615 { |
| 616 CYG_REPORT_FUNCTION(); | |
| 2 | 617 CYG_REPORT_FUNCARG1("vector=%d", vector); |
| 0 | 618 |
| 2 | 619 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 620 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 621 |
| 622 CYG_INSTRUMENT_INTR(MASK, vector, 0); | |
| 623 | |
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624 CYG_INTERRUPT_STATE old_ints; |
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625 |
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626 HAL_DISABLE_INTERRUPTS(old_ints); |
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627 HAL_INTERRUPT_MASK( vector ); |
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628 HAL_RESTORE_INTERRUPTS(old_ints); |
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629 |
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630 CYG_REPORT_RETURN(); |
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631 } |
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632 |
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633 // ------------------------------------------------------------------------- |
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634 // Mask a specific interrupt in a PIC (but not interrupt safe) |
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635 |
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636 void |
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637 Cyg_Interrupt::mask_interrupt_intunsafe(cyg_vector vector) |
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638 { |
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639 CYG_REPORT_FUNCTION(); |
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640 CYG_REPORT_FUNCARG1("vector=%d", vector); |
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641 |
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643 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
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644 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); |
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645 |
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646 CYG_INSTRUMENT_INTR(MASK, vector, 0); |
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647 |
| 2 | 648 HAL_INTERRUPT_MASK( vector ); |
| 649 | |
| 650 CYG_REPORT_RETURN(); | |
| 0 | 651 } |
| 652 | |
| 653 // ------------------------------------------------------------------------- | |
| 654 // Clear PIC mask | |
| 655 | |
| 2 | 656 void |
| 657 Cyg_Interrupt::unmask_interrupt(cyg_vector vector) | |
| 0 | 658 { |
| 659 CYG_REPORT_FUNCTION(); | |
| 660 | |
| 2 | 661 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 662 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 663 |
| 664 CYG_INSTRUMENT_INTR(UNMASK, vector, 0); | |
| 665 | |
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666 CYG_INTERRUPT_STATE old_ints; |
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667 |
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668 HAL_DISABLE_INTERRUPTS(old_ints); |
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669 HAL_INTERRUPT_UNMASK( vector ); |
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670 HAL_RESTORE_INTERRUPTS(old_ints); |
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671 |
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672 CYG_REPORT_RETURN(); |
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673 } |
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674 |
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675 |
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676 // ------------------------------------------------------------------------- |
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677 // Clear PIC mask (but not interrupt safe) |
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678 |
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679 void |
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680 Cyg_Interrupt::unmask_interrupt_intunsafe(cyg_vector vector) |
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681 { |
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682 CYG_REPORT_FUNCTION(); |
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683 |
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684 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
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685 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); |
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686 |
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687 CYG_INSTRUMENT_INTR(UNMASK, vector, 0); |
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688 |
| 0 | 689 HAL_INTERRUPT_UNMASK( vector ); |
| 2 | 690 |
| 691 CYG_REPORT_RETURN(); | |
| 0 | 692 } |
| 693 | |
| 694 | |
| 695 // ------------------------------------------------------------------------- | |
| 696 // Acknowledge interrupt at PIC | |
| 697 | |
| 2 | 698 void |
| 699 Cyg_Interrupt::acknowledge_interrupt(cyg_vector vector) | |
| 0 | 700 { |
| 701 // CYG_REPORT_FUNCTION(); | |
| 702 | |
| 2 | 703 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 704 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 705 |
| 706 CYG_INSTRUMENT_INTR(ACK, vector, 0); | |
| 707 | |
| 708 HAL_INTERRUPT_ACKNOWLEDGE( vector ); | |
| 709 } | |
| 710 | |
| 711 // ------------------------------------------------------------------------- | |
| 712 // Change interrupt detection at PIC | |
| 713 | |
| 2 | 714 void |
| 715 Cyg_Interrupt::configure_interrupt( | |
| 0 | 716 cyg_vector vector, // vector to control |
| 717 cyg_bool level, // level or edge triggered | |
| 718 cyg_bool up // hi/lo level, rising/falling edge | |
| 719 ) | |
| 720 { | |
| 721 CYG_REPORT_FUNCTION(); | |
| 2 | 722 CYG_REPORT_FUNCARG3("vector = %d, level = %d, up = %d", vector, level, |
| 723 up); | |
| 0 | 724 |
| 2 | 725 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 726 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 727 |
| 728 CYG_INSTRUMENT_INTR(CONFIGURE, vector, (level<<1)|up); | |
| 729 | |
| 730 HAL_INTERRUPT_CONFIGURE( vector, level, up ); | |
| 2 | 731 |
| 732 CYG_REPORT_RETURN(); | |
| 0 | 733 } |
| 734 | |
| 735 // ------------------------------------------------------------------------- | |
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736 // SMP support for setting/getting interrupt CPU |
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737 |
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738 #ifdef CYGPKG_KERNEL_SMP_SUPPORT |
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739 |
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740 void |
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741 Cyg_Interrupt::set_cpu( |
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742 cyg_vector vector, // vector to control |
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743 HAL_SMP_CPU_TYPE cpu // CPU to set |
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744 ) |
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745 { |
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746 CYG_REPORT_FUNCTION(); |
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747 CYG_REPORT_FUNCARG2("vector = %d, cpu = %d", vector, cpu ); |
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748 |
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749 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
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750 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); |
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751 |
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752 CYG_INSTRUMENT_INTR(SET_CPU, vector, cpu); |
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753 |
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754 HAL_INTERRUPT_SET_CPU( vector, cpu ); |
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755 |
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756 CYG_REPORT_RETURN(); |
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757 } |
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758 |
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759 HAL_SMP_CPU_TYPE |
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760 Cyg_Interrupt::get_cpu( |
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761 cyg_vector vector // vector to control |
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762 ) |
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763 { |
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764 CYG_REPORT_FUNCTION(); |
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765 CYG_REPORT_FUNCARG1("vector = %d", vector); |
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766 |
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767 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
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768 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); |
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769 |
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770 HAL_SMP_CPU_TYPE cpu = 0; |
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771 |
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772 HAL_INTERRUPT_GET_CPU( vector, cpu ); |
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773 |
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774 CYG_INSTRUMENT_INTR(GET_CPU, vector, cpu); |
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775 |
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776 CYG_REPORT_RETURN(); |
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777 |
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778 return cpu; |
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779 } |
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780 |
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781 #endif |
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782 |
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783 // ------------------------------------------------------------------------- |
| 0 | 784 // EOF intr/intr.cxx |
