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annotate packages/hal/mips/ref4955/current/include/platform.inc @ 208:e0c0827131d1 ecos

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Merge from eCos master repository on 2002-05-20-20:11:54-BST
author jlarmour
date Mon, 20 May 2002 22:19:26 +0000
parents d2f49caf9e38
children d2c90368aeef
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1 #ifndef CYGONCE_HAL_PLATFORM_INC
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2 #define CYGONCE_HAL_PLATFORM_INC
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3 ##=============================================================================
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4 ##
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5 ## platform.inc
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6 ##
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7 ## REF4955/TX4955 board assembler header file
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8 ##
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9 ##=============================================================================
208
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10 #####ECOSGPLCOPYRIGHTBEGIN####
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11 # -------------------------------------------
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12 # This file is part of eCos, the Embedded Configurable Operating System.
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13 # Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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14 #
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15 # eCos is free software; you can redistribute it and/or modify it under
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16 # the terms of the GNU General Public License as published by the Free
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17 # Software Foundation; either version 2 or (at your option) any later version.
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18 #
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19 # eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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20 # WARRANTY; without even the implied warranty of MERCHANTABILITY or
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21 # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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22 # for more details.
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23 #
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24 # You should have received a copy of the GNU General Public License along
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25 # with eCos; if not, write to the Free Software Foundation, Inc.,
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26 # 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 #
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28 # As a special exception, if other files instantiate templates or use macros
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29 # or inline functions from this file, or you compile this file and link it
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30 # with other works to produce a work based on this file, this file does not
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31 # by itself cause the resulting work to be covered by the GNU General Public
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32 # License. However the source code for this file must still be made available
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33 # in accordance with section (3) of the GNU General Public License.
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34 #
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35 # This exception does not invalidate any other reasons why a work based on
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36 # this file might be covered by the GNU General Public License.
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37 #
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38 # Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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39 # at http://sources.redhat.com/ecos/ecos-license
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40 # -------------------------------------------
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41 #####ECOSGPLCOPYRIGHTEND####
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42 ##=============================================================================
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43 #######DESCRIPTIONBEGIN####
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44 ##
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45 ## Author(s): nickg
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46 ## Contributors:nickg,jskov
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47 ## Date: 2000-05-15
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48 ## Purpose: REF4955/TX4955 board definitions.
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49 ## Description: This file contains various definitions and macros that are
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50 ## useful for writing assembly code for the REF4955/TX4955 board.
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51 ## Usage:
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52 ## #include <cyg/hal/platform.inc>
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53 ## ...
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54 ##
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55 ##
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56 ######DESCRIPTIONEND####
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57 ##
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58 ##=============================================================================
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59
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60 #include <cyg/hal/mips.inc>
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61 #include <cyg/hal/plf_defs.inc>
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62
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63
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64 #------------------------------------------------------------------------------
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65 # Macro for copying vectors to RAM if necessary.
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66 #if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
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67
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68 .macro hal_vectors_init
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69 # If we don~t play nice with a ROM monitor, copy the required
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70 # vectors into the proper location.
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71 la t0,0x80000000 # dest addr
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72 la t1,utlb_vector # source addr
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73 la t3,utlb_vector_end # end dest addr
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74 1:
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75 lw v0,0(t1) # get word
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76 addi t1,t1,4
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77 sw v0,0(t0) # write word
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78 addi t0,t0,4
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79 bne t1,t3,1b
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80 nop
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81
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82 la t0,0x80000180 # dest addr
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83 la t1,other_vector # source addr
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84 la t3,other_vector_end # end dest addr
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85 1:
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86 lw v0,0(t1) # get word
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87 addi t1,t1,4
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88 sw v0,0(t0) # write word
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89 addi t0,t0,4
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90 bne t1,t3,1b
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91 nop
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92
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93 .set mips3 # Set ISA to MIPS 3 to allow cache insns
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94 # Now clear the region in the caches
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95 la t0,0x80000000 # dest addr
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96 ori t1,t0,0x200 # source addr
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97 1: cache 0x01,0(t0) # Flush word from data cache
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98 cache 0x01,1(t0)
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99 cache 0x01,2(t0)
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100 cache 0x01,3(t0)
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101 nop
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102 cache 0x00,0(t0) # Invalidate icache for word
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103 cache 0x00,1(t0)
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104 cache 0x00,2(t0)
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105 cache 0x00,3(t0)
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106 nop
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107 addi t0,t0,0x20
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108 bne t0,t1,1b
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109 nop
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110 .set mips0 # reset ISA to default
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111
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112 .endm
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113
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114 #else
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115
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116 .macro hal_vectors_init
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117 .endm
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118
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119 #endif
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120
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121 #------------------------------------------------------------------------------
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122 # Monitor initialization.
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123
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124 #ifndef CYGPKG_HAL_MIPS_MON_DEFINED
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125
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126 #if defined(CYG_HAL_STARTUP_ROM) || \
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127 ( defined(CYG_HAL_STARTUP_RAM) && \
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128 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
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129
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130 # If we are starting up from ROM, or we are starting in
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131 # RAM and NOT using a ROM monitor, initialize the VSR table.
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132
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133 .macro hal_mon_init
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134 hal_vectors_init
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135 # Set default exception VSR for all vectors
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136 ori a0,zero,CYGNUM_HAL_VSR_COUNT
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137 la a1,__default_exception_vsr
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138 la a2,hal_vsr_table
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139 1: sw a1,0(a2)
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140 addi a2,a2,4
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141 addi a0,a0,-1
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142 bne a0,zero,1b
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143 nop
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144
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145 # Now set special VSRs
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146 la a0,hal_vsr_table
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147 # Set interrupt VSR
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148 la a1,__default_interrupt_vsr
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149 sw a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0)
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150 # Add special handler on breakpoint vector to allow GDB and
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151 # GCC to both use 'break' without conflicts.
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152 la a1,__break_vsr_springboard
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153 sw a1,CYGNUM_HAL_VECTOR_BREAKPOINT*4(a0)
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154 # Set exception handler on special vectors
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155 # FIXME: Should use proper definitions
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156 la a1,__default_exception_vsr
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157 sw a1,32*4(a0) # debug
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158 sw a1,33*4(a0) # utlb
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159 sw a1,34*4(a0) # nmi
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160 .endm
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161
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162 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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163
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164 # Initialize the VSR table entries
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165 # We only take control of the interrupt vector,
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166 # the rest are left to the ROM for now...
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167
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168 .macro hal_mon_init
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169 hal_vectors_init
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170 # Set interrupt VSR
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171 la a0,hal_vsr_table
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172 la a1,__default_interrupt_vsr
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173 sw a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0)
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174 .endm
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175
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176 #else
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177
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178 .macro hal_mon_init
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179 hal_vectors_init
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180 .endm
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181
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182 #endif
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183
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184 #define CYGPKG_HAL_MIPS_MON_DEFINED
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185 #endif
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186
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187 #------------------------------------------------------------------------------
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188
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189 #if !defined(CYG_HAL_STARTUP_RAM)
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190 .macro hal_memc_init
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191 // Only initialize the SDRAM controller when running in ROM
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192 .extern hal_memc_setup
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193 lar t0,hal_memc_setup
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194 jalr t0
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195 nop
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196 .endm
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197 #define CYGPKG_HAL_MIPS_MEMC_DEFINED
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198 #endif
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199
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200 #------------------------------------------------------------------------------
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201 # Decide whether the VSR table is defined externally, or is to be defined
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202 # here.
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203
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204 ## ISR tables are defined in platform.S
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205 #define CYG_HAL_MIPS_ISR_TABLES_DEFINED
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206
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207 ## VSR table is at a fixed RAM address defined by the linker script
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208 #define CYG_HAL_MIPS_VSR_TABLE_DEFINED
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209
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210 ##-----------------------------------------------------------------------------
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211 ## For chaining, use the calculated cause vector number.
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212
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213 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
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214 .macro hal_intc_translate inum,vnum
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215 move \vnum,\inum # Vector == interrupt number
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216 .endm
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217 #define CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
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218 #endif
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219
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220 ##-----------------------------------------------------------------------------
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221 #ifdef CYG_STARTUP_ROM
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222
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223 ## Initial SR value for use in ROM:
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224 ## CP0 usable
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225 ## Vectors in RAM
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226 ## FP registers are 32 bit
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227 ## All hw ints disabled
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228 #define INITIAL_SR 0x30000000
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229
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230 #else
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231
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232 ## Initial SR value for use standalone:
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233 ## CP0 usable
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234 ## Vectors to RAM
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235 ## FP registers are 32 bit
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236 ## All hw ints disabled
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237 #define INITIAL_SR 0x30000000
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238
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239 #endif
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240
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241 #------------------------------------------------------------------------------
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242 #endif // ifndef CYGONCE_HAL_PLATFORM_INC
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243 # end of platform.inc