Mercurial > flash_v2
annotate packages/hal/arm/arch/current/src/vectors.S @ 66:bf00f99aec69 ecos-sw-2000-02-02
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| author | jlarmour |
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| date | Wed, 02 Feb 2000 19:57:02 +0000 |
| parents | c38311975d4f |
| children | c5536bad4c24 |
| rev | line source |
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| 2 | 1 // #======================================================================== |
| 2 // # | |
| 3 // # vectors.S | |
| 4 // # | |
| 5 // # ARM exception vectors | |
| 6 // # | |
| 7 // #======================================================================== | |
| 8 // ####COPYRIGHTBEGIN#### | |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Red Hat eCos Public License |
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12 // Version 1.1 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://www.redhat.com/ |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Configurable Operating System, |
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22 // released September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Red Hat. |
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25 // Portions created by Red Hat are |
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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27 // All Rights Reserved. |
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28 // ------------------------------------------- |
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29 // |
| 2 | 30 // ####COPYRIGHTEND#### |
| 31 // #======================================================================== | |
| 32 // ######DESCRIPTIONBEGIN#### | |
| 33 // # | |
| 34 // # Author(s): nickg, gthomas | |
| 35 // # Contributors: nickg, gthomas | |
| 36 // # Date: 1999-02-20 | |
| 37 // # Purpose: ARM exception vectors | |
| 38 // # Description: This file defines the code placed into the exception | |
| 39 // # vectors. It also contains the first level default VSRs | |
| 40 // # that save and restore state for both exceptions and | |
| 41 // # interrupts. | |
| 42 // # | |
| 43 // #####DESCRIPTIONEND#### | |
| 44 // # | |
| 45 // #======================================================================== | |
| 46 | |
| 47 #include <pkgconf/hal.h> | |
| 48 #include <pkgconf/hal_arm.h> | |
| 49 #ifdef CYGPKG_KERNEL // no CDL yet | |
| 50 #include <pkgconf/kernel.h> | |
| 51 #else | |
| 52 # undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
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53 # undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
| 2 | 54 #endif |
| 55 #include <cyg/hal/hal_platform_setup.h> | |
| 56 | |
| 57 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 58 // The CDL should enforce this | |
| 59 #undef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 60 #endif | |
| 61 | |
| 62 #include "arm.inc" | |
| 63 | |
| 64 #define FUNC_START(name) \ | |
| 65 .globl _name; \ | |
| 66 _name: | |
| 67 | |
| 68 #define PTR(name) \ | |
| 69 .##name: .word name | |
| 70 | |
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71 #ifdef CYGHWR_HAL_ARM_HAS_MMU |
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72 #define UNMAPPED(x) ((x)-__exception_handlers) |
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73 #else |
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74 #define UNMAPPED(x) (x) |
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75 #endif |
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76 |
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77 #define UNMAPPED_PTR(name) \ |
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78 .##name: .word UNMAPPED(name) |
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79 |
| 2 | 80 |
| 81 .file "vectors.S" | |
| 82 | |
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83 |
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84 // CYGHWR_LED_MACRO can be defined in hal_platform_setup.h. It's free to |
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85 // use r0+r1. Argument is in "\x" - cannot use macro arguments since the |
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86 // macro may contain #-chars and use of arguments cause these to be |
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87 // interpreted as CPP stringify operators. |
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88 // See example in PID hal_platform_setup.h. |
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89 #ifndef CYGHWR_LED_MACRO |
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90 #define CYGHWR_LED_MACRO |
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91 #endif |
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92 |
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93 .macro LED x |
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94 CYGHWR_LED_MACRO |
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95 .endm |
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96 |
| 2 | 97 |
| 98 //========================================================================== | |
| 99 // Hardware exception vectors. | |
| 100 // This entire section will be copied to location 0x0000 at startup time. | |
| 101 // | |
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102 .code 32 |
| 2 | 103 .section ".vectors","ax" |
| 104 .global __exception_handlers | |
| 105 __exception_handlers: | |
| 106 ldr pc,.reset_vector // 0x00 | |
| 107 ldr pc,.undefined_instruction // 0x04 | |
| 108 ldr pc,.software_interrupt // 0x08 start && software int | |
| 109 ldr pc,.abort_prefetch // 0x0C | |
| 110 ldr pc,.abort_data // 0x10 | |
| 111 .word 0 // unused | |
| 112 ldr pc,.IRQ // 0x18 | |
| 113 ldr pc,.FIQ // 0x1C | |
| 114 | |
| 115 // The layout of these pointers should match the vector table above since | |
| 116 // they are copied in pairs. | |
| 117 .global vectors | |
| 118 vectors: | |
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119 UNMAPPED_PTR(reset_vector) // 0x20 |
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120 PTR(undefined_instruction) // 0x24 |
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121 PTR(software_interrupt) // 0x28 |
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122 PTR(abort_prefetch) // 0x2C |
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123 PTR(abort_data) // 0x30 |
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124 .word 0 // 0x34 |
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125 PTR(IRQ) // 0x38 |
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126 PTR(FIQ) // 0x3c |
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127 PTR(start) // This is copied to 0x28 for bootup // 0x40 |
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128 // location 0x40 is used for storing DRAM size if known |
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129 // for some platforms. |
| 2 | 130 |
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131 // Other vectors |
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132 .balign 16 // Should be at 0x50 |
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133 .balign 32 |
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134 |
| 2 | 135 .text |
| 136 // Startup code which will get the machine into supervisor mode | |
| 137 .global reset_vector | |
| 138 .type reset_vector,function | |
| 139 reset_vector: | |
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140 PLATFORM_SETUP1 // Early stage platform initialization |
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141 // which can set DRAM size at 0x40 |
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142 // see <cyg/hal/hal_platform_setup.h> |
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143 |
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144 // Come here to reset board |
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145 warm_reset: |
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146 |
| 2 | 147 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 148 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 149 mrs r7,cpsr // move back to IRQ mode | |
| 150 and r7,r7,#CPSR_MODE_BITS | |
| 151 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 152 beq start | |
| 153 #endif | |
| 154 | |
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155 // We cannot access any LED registers until after PLATFORM_SETUP1 |
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156 LED 7 |
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157 |
| 2 | 158 mov r0,#0 // move vectors |
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159 // We cannot perform a store until after PLATFORM_SETUP1 |
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160 str r0, [r0,#0x40] // DRAM size to zero => unknown |
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161 |
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162 ldr r1,=__exception_handlers |
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163 #ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
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164 // Wait with this if stubs are included (see further down). |
| 2 | 165 ldr r2,[r1,#0x04] // undefined instruction |
| 166 str r2,[r0,#0x04] | |
| 167 ldr r2,[r1,#0x24] | |
| 168 str r2,[r0,#0x24] | |
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169 #endif |
| 2 | 170 ldr r2,[r1,#0x08] // software interrupt |
| 171 str r2,[r0,#0x08] | |
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172 |
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173 |
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174 #if defined(CYG_HAL_STARTUP_RAM) |
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175 // Ugly hack to get into supervisor mode |
| 2 | 176 ldr r2,[r1,#0x40] |
| 177 str r2,[r0,#0x28] | |
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178 |
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179 LED 6 |
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180 |
| 2 | 181 swi // switch to supervisor mode |
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182 #endif |
| 2 | 183 |
| 184 // ========================================================================= | |
| 185 // Real startup code. We jump here from the reset vector to set up the world. | |
| 186 .globl start | |
| 187 start: | |
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188 |
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189 LED 5 |
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190 |
| 2 | 191 #if defined(CYG_HAL_STARTUP_RAM) && \ |
| 192 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 193 // If we get restarted, hang here to avoid corrupting memory | |
| 194 ldr r0,.init_flag | |
| 195 ldr r1,[r0] | |
| 196 1: cmp r1,#0 | |
| 197 bne 1b | |
| 198 ldr r1,init_done | |
| 199 str r1,[r0] | |
| 200 #endif | |
| 201 | |
| 202 // Reset software interrupt pointer | |
| 203 mov r0,#0 // move vectors | |
| 204 ldr r1,.__exception_handlers | |
| 205 #if defined(CYG_HAL_STARTUP_RAM) && \ | |
| 206 !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) | |
| 207 cmp r7,#CPSR_SUPERVISOR_MODE | |
| 208 beq 10f | |
| 209 #endif | |
| 210 ldr r2,[r1,#0x28] // software interrupt | |
| 211 str r2,[r0,#0x28] | |
| 212 10: | |
| 213 ldr r2,[r1,#0x18] // IRQ | |
| 214 str r2,[r0,#0x18] | |
| 215 ldr r2,[r1,#0x38] | |
| 216 str r2,[r0,#0x38] | |
| 217 ldr r2,[r1,#0x1C] // FIQ | |
| 218 str r2,[r0,#0x1C] | |
| 219 ldr r2,[r1,#0x3C] | |
| 220 str r2,[r0,#0x3C] | |
| 221 ldr r2,[r1,#0x0C] // abort (prefetch) | |
| 222 str r2,[r0,#0x0C] | |
| 223 ldr r2,[r1,#0x2C] | |
| 224 str r2,[r0,#0x2C] | |
| 225 ldr r2,[r1,#0x10] // abort (data) | |
| 226 str r2,[r0,#0x10] | |
| 227 ldr r2,[r1,#0x30] | |
| 228 str r2,[r0,#0x30] | |
| 229 | |
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230 LED 4 |
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231 |
| 2 | 232 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_STUBS) |
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233 // Set up reset vector |
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234 ldr r2,[r1,#0x00] // reset vector intstruction |
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235 str r2,[r0,#0x00] |
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236 ldr r2,=warm_reset |
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237 str r2,[r0,#0x20] |
| 2 | 238 // Relocate [copy] data from ROM to RAM |
| 239 ldr r3,.__rom_data_start | |
| 240 ldr r4,.__ram_data_start | |
| 241 ldr r5,.__ram_data_end | |
| 242 cmp r4,r5 // jump if no data to move | |
| 243 beq 2f | |
| 244 sub r3,r3,#4 // loop adjustments | |
| 245 sub r4,r4,#4 | |
| 246 1: ldr r0,[r3,#4]! // copy info | |
| 247 str r0,[r4,#4]! | |
| 248 cmp r4,r5 | |
| 249 bne 1b | |
| 250 2: | |
| 251 #endif | |
| 252 | |
| 253 // initialize interrupt/exception environments | |
| 254 ldr sp,.__startup_stack | |
| 255 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE) | |
| 256 msr cpsr,r0 | |
| 257 ldr sp,.__exception_stack | |
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258 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_FIQ_MODE) |
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259 msr cpsr,r0 |
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260 ldr sp,.__FIQ_exception_stack |
| 2 | 261 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE) |
| 262 msr cpsr,r0 | |
| 263 ldr sp,.__exception_stack | |
| 264 | |
| 265 // initialize CPSR (machine state register) | |
| 266 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) | |
| 267 msr cpsr,r0 | |
| 268 | |
| 269 // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!! | |
| 270 msr spsr,r0 | |
| 271 | |
| 272 // initialize stack | |
| 273 ldr sp,.__startup_stack | |
| 274 | |
| 275 // clear BSS | |
| 276 ldr r1,.__bss_start | |
| 277 ldr r2,.__bss_end | |
| 278 mov r0,#0 | |
| 279 cmp r1,r2 | |
| 280 beq 2f | |
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281 1: str r0,[r1],#4 |
| 2 | 282 cmp r1,r2 |
| 283 bne 1b | |
| 284 2: | |
| 285 | |
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286 |
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287 LED 3 |
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288 |
| 2 | 289 // Call platform specific hardware initialization |
| 290 bl hal_hardware_init | |
| 291 | |
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292 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
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293 bl initialize_stub |
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294 |
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295 // Now that stub is initialized, change vector. It is possible |
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296 // to single-step through most of the init code, except the below. |
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297 // Put a breakpoint at the call to cyg_hal_invoke_constructors to |
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298 // pass over this bit (s-s depends on internal state in the stub). |
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299 #endif |
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300 |
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301 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) || \ |
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302 defined(CYGIMP_HAL_PROCESS_ALL_EXCEPTIONS) |
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303 mov r0,#0 // move vectors |
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304 ldr r1,=__exception_handlers |
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305 ldr r2,[r1,#0x04] // undefined instruction |
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306 str r2,[r0,#0x04] |
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307 ldr r2,[r1,#0x24] |
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308 str r2,[r0,#0x24] |
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309 #endif |
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310 |
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311 LED 2 |
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312 |
| 2 | 313 // Run through static constructors |
| 314 bl cyg_hal_invoke_constructors | |
| 315 | |
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316 LED 1 |
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317 |
| 2 | 318 // This starts up the eCos kernel |
| 319 bl cyg_start | |
| 320 _start_hang: | |
| 321 b _start_hang | |
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322 .code 32 |
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323 |
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324 .global reset_platform |
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325 .type reset_platform,function |
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326 reset_platform: |
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327 #if defined(CYG_HAL_STARTUP_STUBS) || defined(CYGSEM_HAL_ROM_MONITOR) |
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328 // initialize CPSR (machine state register) |
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329 mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) |
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330 msr cpsr,r0 |
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331 b warm_reset |
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332 #else |
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333 mov r0,#0 |
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334 mov pc,r0 // Jump to reset vector |
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335 #endif |
| 2 | 336 |
| 337 init_done: | |
| 338 .long 0xDEADB00B | |
| 339 | |
| 340 // | |
| 341 // Exception handlers | |
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342 // Assumption: get here from a Supervisor context [mode] |
| 2 | 343 // |
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344 .code 32 |
| 2 | 345 undefined_instruction: |
| 346 ldr sp,.__undef_exception_stack // get good stack | |
| 347 stmfd sp!,{r0,fp,ip,lr} | |
| 348 mrs r0,spsr | |
| 349 stmfd sp!,{r0} | |
| 350 mov ip,sp // save SP which will vanish with | |
| 351 // mode switch | |
| 352 mrs r0,cpsr // switch to Supervisor Mode | |
| 353 bic r0,r0,#CPSR_MODE_BITS | |
| 354 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 355 msr cpsr,r0 // sp,lr are now old values | |
| 356 mov fp,sp | |
| 357 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 358 ldr sp,.__GDB_stack | |
| 359 cmp fp,sp // already on GDB stack? | |
| 360 bhi 10f | |
| 361 ldr r0,.__GDB_stack_base | |
| 362 cmp fp,r0 | |
| 363 bls 10f // no - switch to GDB stack | |
| 364 // (already in sp) | |
| 365 mov sp,fp // yes - no switch | |
| 366 10: | |
| 367 #endif | |
| 368 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 369 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 370 ldmfd ip,{r0-r4} // saved registers | |
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371 sub r4,r4,#4 // PC at time of interrupt |
| 2 | 372 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt |
| 373 str r1,[sp,#armreg_r0] // saved R0 | |
| 374 str r2,[sp,#armreg_fp] // saved FP | |
| 375 str r3,[sp,#armreg_ip] // saved IP | |
| 376 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 377 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 378 add r0,ip,#ARMREG_SIZE | |
| 379 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 380 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 381 mov r0,sp | |
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382 bl cyg_hal_report_undefined_instruction |
| 2 | 383 #endif |
| 384 mov v1,#CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION | |
| 385 b call_exception_handler | |
| 386 | |
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387 .code 32 |
| 2 | 388 software_interrupt: |
| 389 sub sp,sp,#ARMREG_SIZE+16 // make space for frame | |
| 390 stmea sp,{r0-r10,fp} // save immediately visible registers | |
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391 mrs r0,spsr |
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392 sub r3,lr,#4 // PC at time of interrupt |
| 2 | 393 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt |
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394 str ip,[sp,#armreg_ip] // saved IP |
| 2 | 395 str r3,[sp,#armreg_pc] // PC at time of interrupt |
| 396 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
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397 add r0,sp,#ARMREG_SIZE+16 |
| 2 | 398 str r0,[sp,#armreg_sp] // SP at time of interrupt |
| 399 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 400 mov r0,sp | |
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401 bl cyg_hal_report_software_interrupt |
| 2 | 402 #endif |
| 403 mov v1,#CYGNUM_HAL_EXCEPTION_INTERRUPT | |
| 404 b call_exception_handler | |
| 405 | |
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406 .code 32 |
| 2 | 407 abort_prefetch: |
| 408 ldr sp,.__undef_exception_stack // get good stack | |
| 409 sub lr,lr,#4 // PC at time of interrupt | |
| 410 stmfd sp!,{r0,fp,ip,lr} | |
| 411 mrs r0,spsr | |
| 412 stmfd sp!,{r0} | |
| 413 mov ip,sp // save SP which will vanish with | |
| 414 // mode switch | |
| 415 mrs r0,cpsr // switch to Supervisor Mode | |
| 416 bic r0,r0,#CPSR_MODE_BITS | |
| 417 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 418 msr cpsr,r0 // sp,lr are now old values | |
| 419 mov fp,sp | |
| 420 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 421 ldr sp,.__GDB_stack | |
| 422 cmp fp,sp // already on GDB stack? | |
| 423 bhi 10f | |
| 424 ldr r0,.__GDB_stack_base | |
| 425 cmp fp,r0 | |
| 426 bls 10f // no - switch to GDB stack | |
| 427 // (already in sp) | |
| 428 mov sp,fp // yes - no switch | |
| 429 10: | |
| 430 #endif | |
| 431 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 432 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 433 ldmfd ip,{r0-r4} // saved registers | |
| 434 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 435 str r1,[sp,#armreg_r0] // saved R0 | |
| 436 str r2,[sp,#armreg_fp] // saved FP | |
| 437 str r3,[sp,#armreg_ip] // saved IP | |
| 438 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 439 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 440 add r0,ip,#ARMREG_SIZE | |
| 441 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 442 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 443 mov r0,sp | |
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444 bl cyg_hal_report_abort_prefetch |
| 2 | 445 #endif |
| 446 mov v1,#CYGNUM_HAL_EXCEPTION_CODE_ACCESS | |
| 447 b call_exception_handler | |
| 448 | |
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449 .code 32 |
| 2 | 450 abort_data: |
| 451 ldr sp,.__undef_exception_stack // get good stack | |
| 452 sub lr,lr,#4 // PC at time of interrupt | |
| 453 stmfd sp!,{r0,fp,ip,lr} | |
| 454 mrs r0,spsr | |
| 455 stmfd sp!,{r0} | |
| 456 mov ip,sp // save SP which will vanish with | |
| 457 // mode switch | |
| 458 mrs r0,cpsr // switch to Supervisor Mode | |
| 459 bic r0,r0,#CPSR_MODE_BITS | |
| 460 orr r0,r0,#CPSR_SUPERVISOR_MODE | |
| 461 msr cpsr,r0 // sp,lr are now old values | |
| 462 mov fp,sp | |
| 463 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 464 ldr sp,.__GDB_stack | |
| 465 cmp fp,sp // already on GDB stack? | |
| 466 bhi 10f | |
| 467 ldr r0,.__GDB_stack_base | |
| 468 cmp fp,r0 | |
| 469 bls 10f // no - switch to GDB stack | |
| 470 // (already in sp) | |
| 471 mov sp,fp // yes - no switch | |
| 472 10: | |
| 473 #endif | |
| 474 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 475 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 476 ldmfd ip,{r0-r4} // saved registers | |
| 477 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 478 str r1,[sp,#armreg_r0] // saved R0 | |
| 479 str r2,[sp,#armreg_fp] // saved FP | |
| 480 str r3,[sp,#armreg_ip] // saved IP | |
| 481 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 482 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 483 add r0,ip,#ARMREG_SIZE | |
| 484 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 485 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 486 mov r0,sp | |
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487 bl cyg_hal_report_abort_data |
| 2 | 488 #endif |
| 489 mov v1,#CYGNUM_HAL_EXCEPTION_DATA_ACCESS | |
| 490 b call_exception_handler | |
| 491 | |
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492 |
| 2 | 493 // |
| 494 // Dispatch an exception handler. | |
| 495 | |
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496 .code 32 |
| 2 | 497 call_exception_handler: |
| 498 str v1,[sp,#armreg_vector] | |
| 499 mov r0,sp | |
| 500 bl exception_handler | |
| 501 #ifdef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS | |
| 502 mov r0,sp | |
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503 bl cyg_hal_report_exception_handler_returned |
| 2 | 504 #endif |
| 505 | |
| 506 // Restore [interrupted] context | |
| 507 mov ip,sp // get stack pointer | |
| 508 | |
| 509 mrs r0,cpsr // move back to IRQ mode | |
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510 orr r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
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511 msr cpsr,r0 |
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512 nop |
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513 nop |
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514 |
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515 ldr lr,[ip,#armreg_lr] |
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516 ldr sp,[sp,#armreg_sp] |
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517 |
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518 bic r0,r0,#CPSR_MODE_BITS |
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519 orr r0,r0,#CPSR_IRQ_MODE |
| 2 | 520 msr cpsr,r0 |
| 521 | |
| 522 mov sp,ip | |
| 523 ldr lr,[sp,#armreg_pc] | |
| 524 ldr r0,[sp,#armreg_cpsr] | |
| 525 ldr ip,[sp,#armreg_ip] | |
| 526 msr spsr,r0 | |
| 527 ldmfd sp,{r0-r10,fp} | |
| 528 | |
| 529 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 530 | |
| 531 // Handle device interrupts | |
| 532 // This is slightly more complicated than the other exception handlers because | |
| 533 // it needs to interface with the kernel (if present). | |
| 534 | |
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535 .code 32 |
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536 FIQ: |
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537 // Note: I use this exception stack while saving the context because |
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538 // the current SP does not seem to be always valid in this CPU mode. |
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539 ldr sp,.__FIQ_exception_stack // get good stack |
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540 sub lr,lr,#4 // PC at time of interrupt |
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541 stmfd sp!,{r0,fp,ip,lr} |
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542 mrs r0,spsr |
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543 stmfd sp!,{r0} |
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544 b handle_IRQ_or_FIQ |
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545 |
| 2 | 546 IRQ: |
| 547 // Note: I use this exception stack while saving the context because | |
| 548 // the current SP does not seem to be always valid in this CPU mode. | |
| 549 ldr sp,.__exception_stack // get good stack | |
| 550 sub lr,lr,#4 // PC at time of interrupt | |
| 551 stmfd sp!,{r0,fp,ip,lr} | |
| 552 mrs r0,spsr | |
| 553 stmfd sp!,{r0} | |
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554 |
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555 handle_IRQ_or_FIQ: |
| 2 | 556 mov ip,sp // save SP which will vanish with |
| 557 // mode switch | |
| 558 mrs r0,cpsr // switch to Supervisor Mode | |
| 559 bic r0,r0,#CPSR_MODE_BITS | |
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560 orr r0,r0,#CPSR_SUPERVISOR_MODE|CPSR_FIQ_DISABLE|CPSR_IRQ_DISABLE |
| 2 | 561 msr cpsr,r0 // sp,lr are now old values |
| 562 mov fp,sp // save old SP | |
| 563 sub sp,sp,#ARMREG_SIZE // make space for frame | |
| 564 stmea sp,{r0-r10,fp} // save immediately visible registers | |
| 565 ldmfd ip,{r0-r4} // saved registers | |
| 566 str r0,[sp,#armreg_cpsr] // CPSR at time of interrupt | |
| 567 str r1,[sp,#armreg_r0] // saved R0 | |
| 568 str r2,[sp,#armreg_fp] // saved FP | |
| 569 str r3,[sp,#armreg_ip] // saved IP | |
| 570 str r4,[sp,#armreg_pc] // PC at time of interrupt | |
| 571 str lr,[sp,#armreg_lr] // LR at time of interrupt | |
| 572 str fp,[sp,#armreg_sp] // SP at time of interrupt | |
| 573 mov v6,sp // Save pointer to register frame | |
| 574 | |
| 575 // mov r0,sp | |
| 576 // bl _show_frame_in | |
| 577 | |
| 578 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 579 // Switch to interrupt stack | |
| 580 ldr r2,.irq_level // current number of nested interrupts | |
| 581 ldr r0,[r2] | |
| 582 add r1,r0,#1 | |
| 583 str r1,[r2] // if was zero, switch stacks | |
| 584 cmp r0,#0 | |
| 585 moveq r1,sp // save old stack pointer | |
| 586 ldreq sp,.__interrupt_stack | |
| 587 stmeqfd sp!,{r1} | |
| 588 10: | |
| 589 #endif | |
| 590 | |
| 591 // The entire CPU state is now stashed on the stack, | |
| 592 // increment the scheduler lock and handle the interrupt | |
| 593 | |
| 594 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 595 .extern cyg_scheduler_sched_lock | |
| 596 ldr r3,.cyg_scheduler_sched_lock | |
| 597 ldr r4,[r3] | |
| 598 add r4,r4,#1 | |
| 599 str r4,[r3] | |
| 600 #endif | |
| 601 | |
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602 mov r0,v6 |
| 2 | 603 bl hal_IRQ_handler // determine interrupt source |
| 604 mov v1,r0 // returned vector # | |
| 605 | |
| 606 #if defined(CYGPKG_KERNEL_INSTRUMENT) && \ | |
| 607 defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 608 ldr r0,=RAISE_INTR // arg0 = type = INTR,RAISE | |
| 609 mov r1,v1 // arg1 = vector | |
| 610 mov r2,#0 // arg2 = 0 | |
| 611 bl cyg_instrument // call instrument function | |
| 612 #endif | |
| 613 | |
| 614 mov r0,v1 // vector # | |
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615 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS |
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616 cmp r0,#0 // ignore spurious interrupts |
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617 beq spurious_IRQ |
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618 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS |
| 2 | 619 ldr r1,.hal_interrupt_data |
| 620 ldr r1,[r1,v1,lsl #2] // handler data | |
| 621 ldr r2,.hal_interrupt_handlers | |
| 622 ldr v3,[r2,v1,lsl #2] // handler (indexed by vector #) | |
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623 mov r2,v6 // register frame (this is necessary |
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624 // for the ISR too, for ^C detection) |
| 2 | 625 |
| 626 mov lr,pc // invoke handler (call indirect | |
| 627 mov pc,v3 // thru v3) | |
| 628 | |
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629 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS |
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630 spurious_IRQ: |
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631 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_IGNORE_SPURIOUS |
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632 |
| 2 | 633 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
| 634 // If we are returning from the last nested interrupt, move back | |
| 635 // to the thread stack. interrupt_end() must be called on the | |
| 636 // thread stack since it potentially causes a context switch. | |
| 637 ldr r2,.irq_level | |
| 638 ldr r3,[r2] | |
| 639 subs r1,r3,#1 | |
| 640 str r1,[r2] | |
| 641 ldreq sp,[sp] // This should be the saved stack pointer | |
| 642 #endif | |
| 643 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 644 // The return value from the handler (in r0) will indicate whether a | |
| 645 // DSR is to be posted. Pass this together with a pointer to the | |
| 646 // interrupt object we have just used to the interrupt tidy up routine. | |
| 647 | |
| 648 ldr r1,.hal_interrupt_objects | |
| 649 ldr r1,[r1,v1,lsl #2] | |
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650 mov r2,v6 // register frame |
| 2 | 651 bl interrupt_end // post any bottom layer handler |
| 652 // threads and call scheduler | |
| 653 #endif | |
| 654 | |
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655 |
| 2 | 656 // mov r0,sp |
| 657 // bl show_frame_out | |
| 658 | |
| 659 mov ip,sp // get stack pointer | |
| 660 | |
| 661 mrs r0,cpsr // move back to IRQ mode | |
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662 orr r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
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663 msr cpsr,r0 |
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664 nop |
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665 nop |
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666 |
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667 ldr lr,[ip,#armreg_lr] |
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668 ldr sp,[sp,#armreg_sp] |
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669 |
| 2 | 670 bic r0,r0,#CPSR_MODE_BITS |
| 671 orr r0,r0,#CPSR_IRQ_MODE | |
| 672 msr cpsr,r0 | |
| 673 | |
| 674 mov sp,ip | |
| 675 ldr lr,[sp,#armreg_pc] | |
| 676 ldr r0,[sp,#armreg_cpsr] | |
| 677 ldr ip,[sp,#armreg_ip] | |
| 678 msr spsr,r0 | |
| 679 ldmfd sp,{r0-r10,fp} | |
| 680 movs pc,lr // restore PC from LR, CPSR from SPSR | |
| 681 | |
| 682 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 683 // Execute pending DSRs the interrupt stack | |
| 684 // Note: this can only be called from code running on a thread stack | |
| 685 .global hal_interrupt_stack_call_pending_DSRs | |
| 686 hal_interrupt_stack_call_pending_DSRs: | |
| 687 stmfd sp!,{r4,r5,lr} | |
| 688 // Disable interrupts | |
| 689 mrs r4,cpsr // disable IRQ's | |
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690 orr r2,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
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691 bic r5,r4,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
| 2 | 692 msr cpsr,r2 |
| 693 // Switch to interrupt stack | |
| 694 mov r3,sp // save old stack pointer | |
| 695 ldr sp,.__interrupt_stack | |
| 696 stmfd sp!,{r3} // stored at top of interrupt stack | |
| 697 ldr r2,.irq_level // current number of nested interrupts | |
| 698 ldr r3,[r2] | |
| 699 add r3,r3,#1 // bump nesting level | |
| 700 str r3,[r2] | |
| 701 msr cpsr,r5 // enable interrupts | |
| 702 | |
| 703 bl cyg_interrupt_call_pending_DSRs | |
| 704 | |
| 705 // Disable interrupts | |
| 706 mrs r1,cpsr // disable IRQ's | |
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707 orr r2,r1,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE |
| 2 | 708 msr cpsr,r2 |
| 709 | |
| 710 // Move back to the thread stack. | |
| 711 ldr r2,.irq_level | |
| 712 ldr r3,[r2] | |
| 713 sub r3,r3,#1 // decrement nesting level | |
| 714 str r3,[r2] | |
| 715 ldr sp,[sp] // This should be the saved stack pointer | |
| 716 msr cpsr,r4 // restore interrupts to original state | |
| 717 | |
| 718 ldmfd sp!,{r4,r5,pc} // return | |
| 719 #endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
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720 |
| 2 | 721 |
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722 // Dummy/support functions |
| 2 | 723 |
| 724 .global __gccmain | |
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725 .global _psr |
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726 .global _sp |
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727 |
| 2 | 728 __gccmain: |
| 729 mov pc,lr | |
| 730 | |
| 731 _psr: | |
| 732 mrs r0,cpsr | |
| 733 mov pc,lr | |
| 734 | |
| 735 _sp: | |
| 736 mov r0,sp | |
| 737 mov pc,lr | |
| 738 | |
| 739 | |
| 740 // | |
| 741 // Pointers to various objects. | |
| 742 // | |
| 743 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 744 PTR(__GDB_stack_base) | |
| 745 PTR(__GDB_stack) | |
| 746 #endif | |
| 747 PTR(__startup_stack) | |
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748 PTR(__FIQ_exception_stack) |
| 2 | 749 PTR(__exception_stack) |
| 750 PTR(__undef_exception_stack) | |
| 751 PTR(__bss_start) | |
| 752 PTR(__bss_end) | |
| 753 PTR(_end) | |
| 754 PTR(__rom_data_start) | |
| 755 PTR(__ram_data_start) | |
| 756 PTR(__ram_data_end) | |
| 757 PTR(hal_interrupt_handlers) | |
| 758 PTR(hal_interrupt_data) | |
| 759 PTR(hal_interrupt_objects) | |
| 760 PTR(__exception_handlers) | |
| 761 PTR(init_flag) | |
| 762 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 763 PTR(cyg_scheduler_sched_lock) | |
| 764 #endif | |
| 765 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 766 PTR(irq_level) | |
| 767 PTR(__interrupt_stack) | |
| 768 #endif | |
| 769 | |
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770 // |
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771 // Identification - useful to find out when a system was configured |
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772 _eCos_id: |
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773 .asciz "eCos : " __DATE__ |
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774 |
| 2 | 775 |
| 776 // ------------------------------------------------------------------------- | |
| 777 // Interrupt vector tables. | |
| 778 // These tables contain the isr, data and object pointers used to deliver | |
| 779 // interrupts to user code. | |
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780 |
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781 // Despite appearances, their sizes are not #defines, but .equ symbols |
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782 // generated by magic without proper dependencies in arm.inc |
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783 // Recompiling will not DTRT without manual intervention. |
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784 |
| 2 | 785 .data |
| 786 | |
| 787 init_flag: | |
| 788 .long 0 | |
| 789 | |
| 790 .extern hal_default_isr | |
| 791 | |
| 792 .globl hal_interrupt_handlers | |
| 793 hal_interrupt_handlers: | |
| 794 .rept CYGNUM_HAL_ISR_COUNT | |
| 795 .long hal_default_isr | |
| 796 .endr | |
| 797 | |
| 798 .globl hal_interrupt_data | |
| 799 hal_interrupt_data: | |
| 800 .rept CYGNUM_HAL_ISR_COUNT | |
| 801 .long 0 | |
| 802 .endr | |
| 803 | |
| 804 .globl hal_interrupt_objects | |
| 805 hal_interrupt_objects: | |
| 806 .rept CYGNUM_HAL_ISR_COUNT | |
| 807 .long 0 | |
| 808 .endr | |
| 809 | |
| 810 // ------------------------------------------------------------------------- | |
| 811 // Temporary interrupt stack | |
| 812 | |
| 813 .section ".bss" | |
| 814 | |
| 815 // Small stacks, only used for saving information between CPU modes | |
| 816 __exception_stack_base: | |
| 817 .rept 32 | |
| 818 .long 0 | |
| 819 .endr | |
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820 __FIQ_exception_stack: |
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821 .rept 32 |
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822 .long 0 |
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823 .endr |
| 2 | 824 __exception_stack: |
| 825 .rept 32 | |
| 826 .long 0 | |
| 827 .endr | |
| 828 __undef_exception_stack: | |
| 829 | |
| 830 // Runtime stack used during all interrupt processing | |
| 831 #ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 832 #define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096 | |
| 833 #endif | |
| 834 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 835 .balign 16 | |
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836 .global cyg_interrupt_stack_base |
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837 cyg_interrupt_stack_base: |
| 2 | 838 __interrupt_stack_base: |
| 839 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 840 .byte 0 | |
| 841 .endr | |
| 842 .balign 16 | |
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843 .global cyg_interrupt_stack |
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844 cyg_interrupt_stack: |
| 2 | 845 __interrupt_stack: |
| 846 irq_level: | |
| 847 .long 0 | |
| 848 #endif | |
| 849 | |
| 850 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS | |
| 851 .balign 16 | |
| 852 __GDB_stack_base: | |
| 853 .rept 0x400 | |
| 854 .byte 0 | |
| 855 .endr | |
| 856 __GDB_stack: | |
| 857 #endif | |
| 858 .balign 16 | |
| 859 __startup_stack_base: | |
| 860 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 861 .rept 512 | |
| 862 #else | |
| 863 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 864 #endif | |
| 865 .byte 0 | |
| 866 .endr | |
| 867 .balign 16 | |
| 868 __startup_stack: | |
| 869 | |
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870 #ifdef PLATFORM_EXTRAS |
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871 #include PLATFORM_EXTRAS |
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872 #endif |
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873 |
| 2 | 874 // -------------------------------------------------------------------------- |
| 875 // end of vectors.S |