Mercurial > flash_v2
annotate packages/hal/arm/arch/current/include/hal_arch.h @ 210:d2c90368aeef
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| author | jlarmour |
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| date | Thu, 23 May 2002 22:59:51 +0000 |
| parents | e0c0827131d1 |
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| rev | line source |
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| 2 | 1 #ifndef CYGONCE_HAL_ARCH_H |
| 2 #define CYGONCE_HAL_ARCH_H | |
| 3 | |
| 4 //========================================================================== | |
| 5 // | |
| 6 // hal_arch.h | |
| 7 // | |
| 8 // Architecture specific abstractions | |
| 9 // | |
| 10 //========================================================================== | |
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11 //####ECOSGPLCOPYRIGHTBEGIN#### |
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12 // ------------------------------------------- |
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13 // This file is part of eCos, the Embedded Configurable Operating System. |
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
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15 // |
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16 // eCos is free software; you can redistribute it and/or modify it under |
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17 // the terms of the GNU General Public License as published by the Free |
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18 // Software Foundation; either version 2 or (at your option) any later version. |
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19 // |
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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23 // for more details. |
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24 // |
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25 // You should have received a copy of the GNU General Public License along |
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26 // with eCos; if not, write to the Free Software Foundation, Inc., |
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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28 // |
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29 // As a special exception, if other files instantiate templates or use macros |
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30 // or inline functions from this file, or you compile this file and link it |
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31 // with other works to produce a work based on this file, this file does not |
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32 // by itself cause the resulting work to be covered by the GNU General Public |
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33 // License. However the source code for this file must still be made available |
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34 // in accordance with section (3) of the GNU General Public License. |
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35 // |
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36 // This exception does not invalidate any other reasons why a work based on |
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37 // this file might be covered by the GNU General Public License. |
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38 // |
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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40 // at http://sources.redhat.com/ecos/ecos-license/ |
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41 // ------------------------------------------- |
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42 //####ECOSGPLCOPYRIGHTEND#### |
| 2 | 43 //========================================================================== |
| 44 //#####DESCRIPTIONBEGIN#### | |
| 45 // | |
| 46 // Author(s): nickg, gthomas | |
| 47 // Contributors: nickg, gthomas | |
| 48 // Date: 1999-02-20 | |
| 49 // Purpose: Define architecture abstractions | |
| 50 // Usage: #include <cyg/hal/hal_arch.h> | |
| 51 | |
| 52 // | |
| 53 //####DESCRIPTIONEND#### | |
| 54 // | |
| 55 //========================================================================== | |
| 56 | |
| 57 #include <pkgconf/hal.h> // To decide on stack usage | |
| 58 #include <cyg/infra/cyg_type.h> | |
| 59 | |
| 60 // | |
| 61 // CPSR Register defines | |
| 62 // | |
| 63 | |
| 64 #define CPSR_IRQ_DISABLE 0x80 // IRQ disabled when =1 | |
| 65 #define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1 | |
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66 #define CPSR_THUMB_ENABLE 0x20 // Thumb mode when =1 |
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67 #define CPSR_FIQ_MODE 0x11 |
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68 #define CPSR_IRQ_MODE 0x12 |
| 2 | 69 #define CPSR_SUPERVISOR_MODE 0x13 |
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70 #define CPSR_UNDEF_MODE 0x1B |
| 2 | 71 |
| 72 #define CPSR_MODE_BITS 0x1F | |
| 73 | |
| 74 #define CPSR_INITIAL (CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) | |
| 75 #define CPSR_THREAD_INITIAL (CPSR_SUPERVISOR_MODE) | |
| 76 | |
| 77 //-------------------------------------------------------------------------- | |
| 78 // Processor saved states: | |
| 79 // The layout of this structure is also defined in "arm.inc", for assembly | |
| 80 // code, which will be generated automatically if this file changes. | |
| 81 | |
| 82 #define HAL_THREAD_CONTEXT_FIRST 0 | |
| 83 #define HAL_THREAD_CONTEXT_R0 (0-HAL_THREAD_CONTEXT_FIRST) | |
| 84 #define HAL_THREAD_CONTEXT_R4 (4-HAL_THREAD_CONTEXT_FIRST) | |
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85 #define HAL_THREAD_CONTEXT_R8 (8-HAL_THREAD_CONTEXT_FIRST) |
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86 #define HAL_THREAD_CONTEXT_R9 (9-HAL_THREAD_CONTEXT_FIRST) |
| 2 | 87 #define HAL_THREAD_CONTEXT_R10 (10-HAL_THREAD_CONTEXT_FIRST) |
| 88 #define HAL_THREAD_CONTEXT_LAST 10 | |
| 89 #define HAL_NUM_THREAD_CONTEXT_REGS (HAL_THREAD_CONTEXT_LAST - \ | |
| 90 HAL_THREAD_CONTEXT_FIRST+1) | |
| 91 | |
| 92 // It seems that r0-r3,r12 are considered scratch by function calls | |
| 93 | |
| 94 typedef struct | |
| 95 { | |
| 96 // These are common to all saved states | |
| 97 cyg_uint32 d[HAL_NUM_THREAD_CONTEXT_REGS] ; // Data regs (r0..r10) | |
| 98 cyg_uint32 fp; // (r11) Frame pointer | |
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99 cyg_uint32 ip; // (r12) |
| 2 | 100 cyg_uint32 sp; // (r13) Stack pointer |
| 101 cyg_uint32 lr; // (r14) Link Reg | |
| 102 cyg_uint32 pc; // (r15) PC place holder | |
| 103 // (never used) | |
| 104 cyg_uint32 cpsr; // Condition Reg | |
| 105 // These are only saved for exceptions and interrupts | |
| 106 cyg_uint32 vector; // Vector number | |
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107 cyg_uint32 svc_lr; // saved svc mode lr |
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108 cyg_uint32 svc_sp; // saved svc mode sp |
| 2 | 109 |
| 110 } HAL_SavedRegisters; | |
| 111 | |
| 112 //------------------------------------------------------------------------- | |
| 113 // Exception handling function. | |
| 114 // This function is defined by the kernel according to this prototype. It is | |
| 115 // invoked from the HAL to deal with any CPU exceptions that the HAL does | |
| 116 // not want to deal with itself. It usually invokes the kernel's exception | |
| 117 // delivery mechanism. | |
| 118 | |
| 119 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); | |
| 120 | |
| 121 //------------------------------------------------------------------------- | |
| 122 // Bit manipulation macros | |
| 123 | |
| 124 externC int hal_lsbindex(int); | |
| 125 externC int hal_msbindex(int); | |
| 126 | |
| 127 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbindex(mask) | |
| 128 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbindex(mask) | |
| 129 | |
| 130 //------------------------------------------------------------------------- | |
| 131 // Context Initialization | |
| 132 // Initialize the context of a thread. | |
| 133 // Arguments: | |
| 134 // _sparg_ name of variable containing current sp, will be changed to new sp | |
| 135 // _thread_ thread object address, passed as argument to entry point | |
| 136 // _entry_ entry point address. | |
| 137 // _id_ bit pattern used in initializing registers, for debugging. | |
| 138 | |
| 139 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ | |
| 140 CYG_MACRO_START \ | |
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141 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_) &~15; \ |
| 2 | 142 register HAL_SavedRegisters *_regs_; \ |
| 143 int _i_; \ | |
| 144 _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \ | |
| 145 for( _i_ = HAL_THREAD_CONTEXT_FIRST; _i_ <= HAL_THREAD_CONTEXT_LAST; \ | |
| 146 _i_++ ) \ | |
| 147 (_regs_)->d[_i_] = (_id_)|_i_; \ | |
| 148 (_regs_)->d[00] = (CYG_WORD)(_thread_); /* R0 = arg1 = thread ptr */ \ | |
| 149 (_regs_)->sp = (CYG_WORD)(_sp_); /* SP = top of stack */ \ | |
| 150 (_regs_)->lr = (CYG_WORD)(_entry_); /* LR = entry point */ \ | |
| 151 (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = [initial] entry point */\ | |
| 152 (_regs_)->cpsr = (CPSR_THREAD_INITIAL); /* PSR = Interrupt enabled */ \ | |
| 153 _sparg_ = (CYG_ADDRESS)_regs_; \ | |
| 154 CYG_MACRO_END | |
| 155 | |
| 156 //-------------------------------------------------------------------------- | |
| 157 // Context switch macros. | |
| 158 // The arguments are pointers to locations where the stack pointer | |
| 159 // of the current thread is to be stored, and from where the sp of the | |
| 160 // next thread is to be fetched. | |
| 161 | |
| 162 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); | |
| 163 externC void hal_thread_load_context( CYG_ADDRESS to ) | |
| 164 __attribute__ ((noreturn)); | |
| 165 | |
| 166 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ | |
| 167 hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \ | |
| 168 (CYG_ADDRESS)_fspptr_); | |
| 169 | |
| 170 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ | |
| 171 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); | |
| 172 | |
| 173 //-------------------------------------------------------------------------- | |
| 174 // Execution reorder barrier. | |
| 175 // When optimizing the compiler can reorder code. In multithreaded systems | |
| 176 // where the order of actions is vital, this can sometimes cause problems. | |
| 177 // This macro may be inserted into places where reordering should not happen. | |
| 178 | |
| 179 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) | |
| 180 | |
| 181 //-------------------------------------------------------------------------- | |
| 182 // Breakpoint support | |
| 183 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen | |
| 184 // if executed. | |
| 185 // HAL_BREAKINST is the value of the breakpoint instruction and | |
| 186 // HAL_BREAKINST_SIZE is its size in bytes. | |
| 187 | |
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188 #define _stringify1(__arg) #__arg |
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189 #define _stringify(__arg) _stringify1(__arg) |
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190 |
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191 #define HAL_BREAKINST_ARM 0xE7FFDEFE |
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192 #define HAL_BREAKINST_ARM_SIZE 4 |
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193 #define HAL_BREAKINST_THUMB 0xbebe // illegal instruction currently |
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194 #define HAL_BREAKINST_THUMB_SIZE 2 |
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195 |
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196 #ifdef __thumb__ |
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197 |
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198 # define HAL_BREAKPOINT(_label_) \ |
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199 asm volatile (" .code 16;" \ |
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200 " .globl " #_label_ ";" \ |
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201 #_label_":" \ |
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202 " .short " _stringify(HAL_BREAKINST_THUMB) \ |
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203 ); |
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204 |
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205 # define HAL_BREAKINST HAL_BREAKINST_THUMB |
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206 # define HAL_BREAKINST_SIZE HAL_BREAKINST_THUMB_SIZE |
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207 # define HAL_BREAKINST_TYPE cyg_uint16 |
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208 #else // __thumb__ |
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209 |
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210 #define HAL_BREAKPOINT(_label_) \ |
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211 asm volatile (" .globl " #_label_ ";" \ |
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212 #_label_":" \ |
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213 " .word " _stringify(HAL_BREAKINST_ARM) \ |
| 2 | 214 ); |
| 215 | |
| 216 //#define HAL_BREAKINST {0xFE, 0xDE, 0xFF, 0xE7} | |
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217 #define HAL_BREAKINST HAL_BREAKINST_ARM |
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218 #define HAL_BREAKINST_SIZE HAL_BREAKINST_ARM_SIZE |
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219 #define HAL_BREAKINST_TYPE cyg_uint32 |
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220 #endif // __thumb__ |
| 2 | 221 |
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222 |
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223 extern cyg_uint32 __arm_breakinst; |
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224 extern cyg_uint16 __thumb_breakinst; |
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225 #define HAL_BREAKINST_ADDR(x) (((x)==2)? \ |
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226 ((void*)&__thumb_breakinst) : \ |
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227 ((void*)&__arm_breakinst)) |
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228 |
| 2 | 229 //-------------------------------------------------------------------------- |
| 230 // Thread register state manipulation for GDB support. | |
| 231 | |
| 232 // GDB expects the registers in this structure: | |
| 233 // r0..r10, fp, ip, sp, lr, pc - 4 bytes each | |
| 234 // f0..f7 - 12 bytes each (N/A on ARM7) | |
| 235 // fps - 4 bytes (N/A on ARM7) | |
| 236 // ps - 4 bytes | |
| 237 | |
| 238 // Translate a stack pointer as saved by the thread context macros above into | |
| 239 // a pointer to a HAL_SavedRegisters structure. | |
| 240 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ | |
| 241 (_regs_) = (HAL_SavedRegisters *)(_sp_) | |
| 242 | |
| 243 // Copy a set of registers from a HAL_SavedRegisters structure into a | |
| 244 // GDB ordered array. | |
| 245 #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \ | |
| 246 CYG_MACRO_START \ | |
| 247 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ | |
| 248 int _i_; \ | |
| 249 \ | |
| 250 for( _i_ = 0; _i_ <= 10; _i_++ ) \ | |
| 251 _regval_[_i_] = (_regs_)->d[_i_]; \ | |
| 252 \ | |
| 253 _regval_[11] = (_regs_)->fp; \ | |
| 254 _regval_[12] = (_regs_)->ip; \ | |
| 255 _regval_[13] = (_regs_)->sp; \ | |
| 256 _regval_[14] = (_regs_)->lr; \ | |
| 257 _regval_[15] = (_regs_)->pc; \ | |
| 258 _regval_[25] = (_regs_)->cpsr; \ | |
| 259 for( _i_ = 0; _i_ < 8; _i_++ ) \ | |
| 260 _regval_[_i_+16] = 0; \ | |
| 261 CYG_MACRO_END | |
| 262 | |
| 263 // Copy a GDB ordered array into a HAL_SavedRegisters structure. | |
| 264 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ | |
| 265 CYG_MACRO_START \ | |
| 266 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ | |
| 267 int _i_; \ | |
| 268 \ | |
| 269 for( _i_ = 0; _i_ <= 10; _i_++ ) \ | |
| 270 (_regs_)->d[_i_] = _regval_[_i_]; \ | |
| 271 \ | |
| 272 (_regs_)->fp = _regval_[11]; \ | |
| 273 (_regs_)->ip = _regval_[12]; \ | |
| 274 (_regs_)->sp = _regval_[13]; \ | |
| 275 (_regs_)->lr = _regval_[14]; \ | |
| 276 (_regs_)->pc = _regval_[15]; \ | |
| 277 (_regs_)->cpsr = _regval_[25]; \ | |
| 278 CYG_MACRO_END | |
| 279 | |
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280 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) |
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281 #define HAL_GET_PROFILE_INFO( _thepc_, _thesp_ ) \ |
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282 CYG_MACRO_START \ |
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283 extern HAL_SavedRegisters *hal_saved_interrupt_state; \ |
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284 if ( hal_saved_interrupt_state ) { \ |
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285 (_thepc_) = (char *)(hal_saved_interrupt_state->pc); \ |
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286 (_thesp_) = (char *)(hal_saved_interrupt_state->sp); \ |
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287 } \ |
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288 CYG_MACRO_END |
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289 #endif |
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290 |
| 2 | 291 //-------------------------------------------------------------------------- |
| 292 // HAL setjmp | |
| 293 | |
| 294 #define CYGARC_JMP_BUF_SIZE 16 // Actually 11, but some room left over | |
| 295 | |
| 296 typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE]; | |
| 297 | |
| 298 externC int hal_setjmp(hal_jmp_buf env); | |
| 299 externC void hal_longjmp(hal_jmp_buf env, int val); | |
| 300 | |
| 301 | |
| 302 //-------------------------------------------------------------------------- | |
| 303 // Idle thread code. | |
| 304 // This macro is called in the idle thread loop, and gives the HAL the | |
| 305 // chance to insert code. Typical idle thread behaviour might be to halt the | |
| 306 // processor. | |
| 307 | |
| 308 externC void hal_idle_thread_action(cyg_uint32 loop_count); | |
| 309 | |
| 310 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) | |
| 311 | |
| 312 //--------------------------------------------------------------------------- | |
| 313 | |
| 314 // Minimal and sensible stack sizes: the intention is that applications | |
| 315 // will use these to provide a stack size in the first instance prior to | |
| 316 // proper analysis. Idle thread stack should be this big. | |
| 317 | |
| 318 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. | |
| 319 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. | |
| 320 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! | |
| 321 | |
| 322 // This is not a config option because it should not be adjusted except | |
| 323 // under "enough rope" sort of disclaimers. | |
| 324 | |
| 325 // A minimal, optimized stack frame, rounded up - no autos | |
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326 #define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 20) |
| 2 | 327 |
| 328 // Stack needed for a context switch: this is implicit in the estimate for | |
| 329 // interrupts so not explicitly used below: | |
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330 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 20) |
| 2 | 331 |
| 332 // Interrupt + call to ISR, interrupt_end() and the DSR | |
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333 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE \ |
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334 ((4 * 20) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE) |
| 2 | 335 |
| 336 // Space for the maximum number of nested interrupts, plus room to call functions | |
| 337 #define CYGNUM_HAL_MAX_INTERRUPT_NESTING 4 | |
| 338 | |
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339 #define CYGNUM_HAL_STACK_SIZE_MINIMUM \ |
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340 (CYGNUM_HAL_MAX_INTERRUPT_NESTING * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \ |
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341 2 * CYGNUM_HAL_STACK_FRAME_SIZE) |
| 2 | 342 |
| 343 #define CYGNUM_HAL_STACK_SIZE_TYPICAL \ | |
| 344 (CYGNUM_HAL_STACK_SIZE_MINIMUM + \ | |
| 345 16 * CYGNUM_HAL_STACK_FRAME_SIZE) | |
| 346 | |
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347 //-------------------------------------------------------------------------- |
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348 // Macros for switching context between two eCos instances (jump from |
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349 // code in ROM to code in RAM or vice versa). |
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350 #define CYGARC_HAL_SAVE_GP() |
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351 #define CYGARC_HAL_RESTORE_GP() |
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352 |
| 2 | 353 #endif // CYGONCE_HAL_ARCH_H |
| 354 // End of hal_arch.h |