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annotate packages/hal/mips/tx39/current/include/var_cache.h @ 210:d2c90368aeef

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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children
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1 #ifndef CYGONCE_IMP_CACHE_H
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2 #define CYGONCE_IMP_CACHE_H
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3
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4 //=============================================================================
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5 //
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6 // imp_cache.h
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7 //
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8 // HAL cache control API
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9 //
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10 //=============================================================================
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11 //####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
208
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg
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47 // Contributors: nickg
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48 // Date: 1998-02-17
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49 // Purpose: Cache control API
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // cache control operations.
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52 // Usage:
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53 // #include <cyg/hal/imp_cache.h>
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54 // ...
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55 //
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56 //
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57 //####DESCRIPTIONEND####
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58 //
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59 //=============================================================================
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60
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61 #include <pkgconf/hal.h>
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62 #include <cyg/infra/cyg_type.h>
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63
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64 #include <cyg/hal/plf_cache.h>
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65
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66 //=============================================================================
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67 // Toshiba TX3904
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68
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69 #ifdef CYGPKG_HAL_MIPS_TX3904
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70
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71 //-----------------------------------------------------------------------------
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72 // Cache dimensions
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73
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74 // Data cache
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75 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
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76 #define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
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77 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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78
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79 // Instruction cache
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80 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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81 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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82 #define HAL_ICACHE_WAYS 1 // Associativity of the cache
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83
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84 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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85 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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86
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87 //-----------------------------------------------------------------------------
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88 // Global control of data cache
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89
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90 // Enable the data cache
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91 // This uses a bit in the config register, which is TX39 specific.
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92 #define HAL_DCACHE_ENABLE_DEFINED
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93 #define HAL_DCACHE_ENABLE() \
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94 { \
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95 asm volatile ("mfc0 $2,$3;" \
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96 "ori $2,$2,0x0010;" \
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97 "mtc0 $2,$3;" \
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98 : \
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99 : \
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100 : "$2" \
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101 ); \
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102 \
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103 }
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104
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105 // Disable the data cache
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106 #define HAL_DCACHE_DISABLE_DEFINED
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107 #define HAL_DCACHE_DISABLE() \
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108 { \
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109 asm volatile ("mfc0 $2,$3;" \
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110 "la $3,0xFFFFFFEF;" \
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111 "and $2,$2,$3;" \
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112 "mtc0 $2,$3;" \
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113 : \
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114 : \
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115 : "$2", "$3" \
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116 ); \
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117 \
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118 }
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119
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120
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121 // Invalidate the entire cache
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122 // The TX39 only has hit-invalidate on the DCACHE, not
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123 // index-invalidate, so we cannot just empty the cache out without
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124 // knowing what is in it. This is annoying. So, the best we can do is
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125 // fill the cache with data that is unlikely to be there
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126 // otherwise. Hence we read bytes from the ROM space since this is
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127 // most likely to be code, and will not get out of sync even if it is not.
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128 #define HAL_DCACHE_INVALIDATE_ALL_DEFINED
130
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129 #define HAL_DCACHE_INVALIDATE_ALL() \
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130 { \
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131 volatile CYG_BYTE *addr = (CYG_BYTE *)(0x9fc00000); \
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132 volatile CYG_BYTE tmp = 0; \
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133 int i; \
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134 for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE ) \
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135 { \
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136 tmp = addr[i]; \
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137 } \
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138 }
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139
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140 // Synchronize the contents of the cache with memory.
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141 #define HAL_DCACHE_SYNC_DEFINED
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142 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
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143
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144 // Set the data cache refill burst size
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145 //#define HAL_DCACHE_BURST_SIZE(_size_)
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146
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147 // Set the data cache write mode
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148 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
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149
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150 //#define HAL_DCACHE_WRITETHRU_MODE 0
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151 //#define HAL_DCACHE_WRITEBACK_MODE 1
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152
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153 // Load the contents of the given address range into the data cache
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154 // and then lock the cache so that it stays there.
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155 #define HAL_DCACHE_LOCK_DEFINED
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156 #define HAL_DCACHE_LOCK(_base_, _size_) \
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157 { \
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158 asm volatile ("mfc0 $2,$7;" \
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159 "ori $2,$2,0x0100;" \
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160 "mtc0 $2,$7;" \
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161 : \
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162 : \
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163 : "$2" \
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164 ); \
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165 }
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166
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167 // Undo a previous lock operation
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168 #define HAL_DCACHE_UNLOCK_DEFINED
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169 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
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170 { \
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171 asm volatile ("mfc0 $2,$7;" \
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172 "la $3,0xFFFFFEFF;" \
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173 "and $2,$2,$3;" \
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174 "mtc0 $2,$7;" \
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175 : \
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176 : \
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177 : "$2", "$3" \
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178 ); \
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179 }
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180
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181 // Unlock entire cache
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182 #define HAL_DCACHE_UNLOCK_ALL_DEFINED
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183 #define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
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184
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185
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186 //-----------------------------------------------------------------------------
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187 // Data cache line control
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188
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189 // Allocate cache lines for the given address range without reading its
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190 // contents from memory.
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191 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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192
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193 // Write dirty cache lines to memory and invalidate the cache entries
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194 // for the given address range.
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195 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
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196 #define HAL_DCACHE_FLUSH_DEFINED // Ensure no default definition
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197
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198 // Write dirty cache lines to memory for the given address range.
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199 //#define HAL_DCACHE_STORE( _base_ , _size_ )
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200 #define HAL_DCACHE_STORE_DEFINED // Disable default definition
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201
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202 //-----------------------------------------------------------------------------
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203 // Global control of Instruction cache
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204
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205 // Enable the instruction cache
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206 // This uses a bit in the config register, which is TX39 specific.
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207 #define HAL_ICACHE_ENABLE_DEFINED
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208 #define HAL_ICACHE_ENABLE() \
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209 { \
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210 asm volatile ("mfc0 $2,$3;" \
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211 "ori $2,$2,0x0020;" \
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212 "mtc0 $2,$3;" \
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213 : \
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214 : \
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215 : "$2" \
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216 ); \
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217 \
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218 }
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219
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220 // Disable the instruction cache
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221 #define HAL_ICACHE_DISABLE_DEFINED
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222 #define HAL_ICACHE_DISABLE() \
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223 { \
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224 asm volatile ("mfc0 $2,$3;" \
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225 "la $3,0xFFFFFFDF;" \
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226 "and $2,$2,$3;" \
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227 "mtc0 $2,$3;" \
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228 "j 1f;" \
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229 "nop;" \
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230 ".balign 16,0;" \
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231 "1:;" \
6
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232 : \
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233 : \
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234 : "$2", "$3" \
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235 ); \
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236 \
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237 }
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238
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239 // Load the contents of the given address range into the instruction cache
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240 // and then lock the cache so that it stays there.
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241 #define HAL_ICACHE_LOCK_DEFINED
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242 #define HAL_ICACHE_LOCK(_base_, _size_) \
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243 { \
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244 asm volatile ("mfc0 $2,$7;" \
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245 "ori $2,$2,0x0200;" \
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246 "mtc0 $2,$7;" \
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247 : \
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248 : \
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249 : "$2" \
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250 ); \
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251 }
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252
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253 // Undo a previous lock operation
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254 #define HAL_ICACHE_UNLOCK_DEFINED
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255 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
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256 { \
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257 asm volatile ("mfc0 $2,$7;" \
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258 "la $3,0xFFFFFDFF;" \
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259 "and $2,$2,$3;" \
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260 "mtc0 $2,$7;" \
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261 : \
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262 : \
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263 : "$2", "$3" \
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264 ); \
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265 }
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266
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267 // Unlock entire cache
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268 #define HAL_ICACHE_UNLOCK_ALL_DEFINED
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269 #define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, HAL_ICACHE_SIZE)
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270
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271 //-----------------------------------------------------------------------------
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272 // Instruction cache line control
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273 // On the TX39, the instruction cache must be disabled to use the index-invalidate
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274 // cache operation.
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275
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276 // Invalidate the entire cache
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277 // This uses the index-invalidate cache operation.
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278 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
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279 #define HAL_ICACHE_INVALIDATE_ALL() \
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280 { \
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281 register CYG_ADDRESS _baddr_ = 0x80000000; \
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282 register CYG_ADDRESS _addr_ = 0x80000000; \
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283 register CYG_WORD _state_; \
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284 HAL_ICACHE_IS_ENABLED(_state_); \
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285 HAL_ICACHE_DISABLE(); \
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286 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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287 { \
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288 asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \
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289 } \
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290 if( _state_ ) HAL_ICACHE_ENABLE(); \
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291 }
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292
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293 // Invalidate cache lines in the given range without writing to memory.
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294 // This uses the index-invalidate cache operation since the TX39 does not
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295 // have hit-invalidate on the instruction cache.
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296 #define HAL_ICACHE_INVALIDATE_DEFINED
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297 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
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298 { \
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299 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
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300 register CYG_WORD _size_ = (_asize_); \
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301 register CYG_WORD _state_; \
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302 HAL_ICACHE_IS_ENABLED(_state_); \
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303 HAL_ICACHE_DISABLE(); \
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304 for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
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305 { \
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306 asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \
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307 } \
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308 if( _state_ ) HAL_ICACHE_ENABLE(); \
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309 }
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310
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311 #endif // CYGPKG_HAL_MIPS_TX3904
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312
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313 //-----------------------------------------------------------------------------
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314 #endif // ifndef CYGONCE_IMP_CACHE_H
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315 // End of imp_cache.h