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annotate packages/kernel/current/tests/kcache1.c @ 210:d2c90368aeef

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Merge from eCos master repository on 2002-05-23-21:39:14-BST
author jlarmour
date Thu, 23 May 2002 22:59:51 +0000
parents e0c0827131d1
children
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1 /*=================================================================
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2 //
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3 // kcache1.c
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4 //
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5 // Cache timing test
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6 //
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7 //==========================================================================
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8 //####ECOSGPLCOPYRIGHTBEGIN####
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9 // -------------------------------------------
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10 // This file is part of eCos, the Embedded Configurable Operating System.
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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12 //
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13 // eCos is free software; you can redistribute it and/or modify it under
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14 // the terms of the GNU General Public License as published by the Free
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15 // Software Foundation; either version 2 or (at your option) any later version.
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16 //
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17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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20 // for more details.
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21 //
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22 // You should have received a copy of the GNU General Public License along
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23 // with eCos; if not, write to the Free Software Foundation, Inc.,
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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25 //
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26 // As a special exception, if other files instantiate templates or use macros
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27 // or inline functions from this file, or you compile this file and link it
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28 // with other works to produce a work based on this file, this file does not
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29 // by itself cause the resulting work to be covered by the GNU General Public
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30 // License. However the source code for this file must still be made available
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31 // in accordance with section (3) of the GNU General Public License.
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32 //
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33 // This exception does not invalidate any other reasons why a work based on
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34 // this file might be covered by the GNU General Public License.
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35 //
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36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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37 // at http://sources.redhat.com/ecos/ecos-license/
208
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38 // -------------------------------------------
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39 //####ECOSGPLCOPYRIGHTEND####
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40 //==========================================================================
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41 //#####DESCRIPTIONBEGIN####
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42 //
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43 // Author(s): dsm
44
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44 // Contributors: dsm, nickg
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45 // Date: 1998-06-18
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46 //####DESCRIPTIONEND####
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47 */
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48
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49 #include <cyg/hal/hal_arch.h> // CYGNUM_HAL_STACK_SIZE_TYPICAL
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50
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51 #include <cyg/kernel/kapi.h>
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52
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53 #include <cyg/infra/testcase.h>
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54
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55 #include <cyg/hal/hal_cache.h>
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56
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57 #if defined(HAL_DCACHE_SIZE) || defined(HAL_UCACHE_SIZE)
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58 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK
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59 #ifdef CYGFUN_KERNEL_API_C
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60
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61 #include <cyg/infra/diag.h>
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62 #include <cyg/hal/hal_intr.h>
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63
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64 // -------------------------------------------------------------------------
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65 // If the HAL does not supply this, we supply our own version
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66
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67 #ifndef HAL_DCACHE_PURGE_ALL
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68 # ifdef HAL_DCACHE_SYNC
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69
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70 #define HAL_DCACHE_PURGE_ALL() HAL_DCACHE_SYNC()
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71
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72 # else
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73
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74 static cyg_uint8 dca[HAL_DCACHE_SIZE + HAL_DCACHE_LINE_SIZE*2];
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75
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76 #define HAL_DCACHE_PURGE_ALL() \
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77 CYG_MACRO_START \
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78 volatile cyg_uint8 *addr = &dca[HAL_DCACHE_LINE_SIZE]; \
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79 volatile cyg_uint8 tmp = 0; \
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80 int i; \
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81 for( i = 0; i < HAL_DCACHE_SIZE; i += HAL_DCACHE_LINE_SIZE ) \
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82 { \
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83 tmp = addr[i]; \
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84 } \
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85 CYG_MACRO_END
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86
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87 # endif
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88 #endif
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89
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90 // -------------------------------------------------------------------------
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91
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92 #define NTHREADS 1
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93 #define STACKSIZE CYGNUM_HAL_STACK_SIZE_TYPICAL
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94
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95 static cyg_handle_t thread[NTHREADS];
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96
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97 static cyg_thread thread_obj[NTHREADS];
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98 static char stack[NTHREADS][STACKSIZE];
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99
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100 #ifndef MAX_STRIDE
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101 #define MAX_STRIDE 64
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102 #endif
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103
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104 volatile char m[(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE)*MAX_STRIDE];
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105
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106 // -------------------------------------------------------------------------
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107
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108 static void time0(register cyg_uint32 stride)
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109 {
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110 register cyg_uint32 j,k;
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111 cyg_tick_count_t count0, count1;
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112 cyg_ucount32 t;
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113 register char c;
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114
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115 count0 = cyg_current_time();
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116
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117 k = 0;
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118 if ( cyg_test_is_simulator )
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119 k = 3960;
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120
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121 for(; k<4000;k++) {
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122 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
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123 c=m[stride*j];
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124 }
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125 }
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126
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127 count1 = cyg_current_time();
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128 t = count1 - count0;
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129 diag_printf("stride=%d, time=%d\n", stride, t);
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130 }
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131
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132 // -------------------------------------------------------------------------
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133
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134 void time1(void)
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135 {
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136 cyg_uint32 i;
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137
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138 for(i=1; i<=MAX_STRIDE; i+=i) {
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139 time0(i);
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140 }
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141 }
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142
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143 // -------------------------------------------------------------------------
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144 // With an ICache invalidate in the middle:
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145 #ifdef HAL_ICACHE_INVALIDATE_ALL
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146 static void time0II(register cyg_uint32 stride)
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147 {
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148 register cyg_uint32 j,k;
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149 cyg_tick_count_t count0, count1;
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150 cyg_ucount32 t;
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151 register char c;
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152
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153 count0 = cyg_current_time();
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154
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155 k = 0;
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156 if ( cyg_test_is_simulator )
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157 k = 3960;
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158
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159 for(; k<4000;k++) {
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160 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
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161 HAL_ICACHE_INVALIDATE_ALL();
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162 c=m[stride*j];
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163 }
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164 }
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165
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166 count1 = cyg_current_time();
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167 t = count1 - count0;
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168 diag_printf("stride=%d, time=%d\n", stride, t);
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169 }
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170
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171 // -------------------------------------------------------------------------
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172
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173 void time1II(void)
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174 {
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175 cyg_uint32 i;
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176
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177 for(i=1; i<=MAX_STRIDE; i+=i) {
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178 time0II(i);
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179 }
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180 }
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181 #endif
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182 // -------------------------------------------------------------------------
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183 // With a DCache invalidate in the middle:
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184 // This is guaranteed to produce bogus timing results since interrupts
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185 // have to be disabled to prevent accidental loss of state.
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186 #ifdef HAL_DCACHE_INVALIDATE_ALL
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187 static void time0DI(register cyg_uint32 stride)
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188 {
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189 register cyg_uint32 j,k;
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190 volatile cyg_tick_count_t count0;
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191 cyg_tick_count_t count1;
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192 cyg_ucount32 t;
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193 register char c;
208
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194 register CYG_INTERRUPT_STATE oldints;
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195
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196 count0 = cyg_current_time();
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197
208
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198 HAL_DISABLE_INTERRUPTS(oldints);
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199 HAL_DCACHE_SYNC();
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200
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201 k = 0;
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202 if ( cyg_test_is_simulator )
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203 k = 3960;
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204
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205 for(; k<4000;k++) {
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206 for(j=0; j<(HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE); j++) {
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207 HAL_DCACHE_INVALIDATE_ALL();
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208 c=m[stride*j];
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209 }
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210 }
208
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211 HAL_RESTORE_INTERRUPTS(oldints);
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212
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213 count1 = cyg_current_time();
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214 t = count1 - count0;
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215 diag_printf("stride=%d, time=%d\n", stride, t);
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216 }
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217
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218 // -------------------------------------------------------------------------
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219
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220 void time1DI(void)
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221 {
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222 cyg_uint32 i;
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223
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224 for(i=1; i<=MAX_STRIDE; i+=i) {
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225 time0DI(i);
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226 }
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227 }
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228 #endif
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229 // -------------------------------------------------------------------------
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230 // This test could be improved by counting number of passes possible
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231 // in a given number of ticks.
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232
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233 static void entry0( cyg_addrword_t data )
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234 {
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235 register CYG_INTERRUPT_STATE oldints;
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236
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237 #ifdef HAL_CACHE_UNIFIED
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238
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239 HAL_DISABLE_INTERRUPTS(oldints);
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240 HAL_DCACHE_PURGE_ALL(); // rely on above definition
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241 HAL_UCACHE_INVALIDATE_ALL();
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242 HAL_UCACHE_DISABLE();
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243 HAL_RESTORE_INTERRUPTS(oldints);
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244 CYG_TEST_INFO("Cache off");
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245 time1();
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246
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247 HAL_DISABLE_INTERRUPTS(oldints);
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248 HAL_DCACHE_PURGE_ALL(); // rely on above definition
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249 HAL_UCACHE_INVALIDATE_ALL();
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250 HAL_UCACHE_ENABLE();
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251 HAL_RESTORE_INTERRUPTS(oldints);
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252 CYG_TEST_INFO("Cache on");
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253 time1();
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254
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255 #ifdef HAL_DCACHE_INVALIDATE_ALL
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256 HAL_DISABLE_INTERRUPTS(oldints);
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257 HAL_DCACHE_PURGE_ALL();
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258 HAL_UCACHE_INVALIDATE_ALL();
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259 HAL_UCACHE_ENABLE();
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260 HAL_RESTORE_INTERRUPTS(oldints);
208
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261 CYG_TEST_INFO("Cache on: invalidate Cache (expect bogus timing)");
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262 time1DI();
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263 #endif
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264
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265 #else // HAL_CACHE_UNIFIED
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266
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267 HAL_DISABLE_INTERRUPTS(oldints);
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268 HAL_DCACHE_PURGE_ALL();
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269 HAL_ICACHE_INVALIDATE_ALL();
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270 HAL_DCACHE_INVALIDATE_ALL();
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271 HAL_ICACHE_DISABLE();
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272 HAL_DCACHE_DISABLE();
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273 HAL_RESTORE_INTERRUPTS(oldints);
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274 CYG_TEST_INFO("Dcache off Icache off");
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275 time1();
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276
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277 HAL_DISABLE_INTERRUPTS(oldints);
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278 HAL_DCACHE_PURGE_ALL();
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279 HAL_ICACHE_INVALIDATE_ALL();
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280 HAL_DCACHE_INVALIDATE_ALL();
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281 HAL_ICACHE_DISABLE();
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282 HAL_DCACHE_ENABLE();
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283 HAL_RESTORE_INTERRUPTS(oldints);
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284 CYG_TEST_INFO("Dcache on Icache off");
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285 time1();
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286
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287 HAL_DISABLE_INTERRUPTS(oldints);
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288 HAL_DCACHE_PURGE_ALL();
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289 HAL_ICACHE_INVALIDATE_ALL();
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290 HAL_DCACHE_INVALIDATE_ALL();
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291 HAL_ICACHE_ENABLE();
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292 HAL_DCACHE_DISABLE();
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293 HAL_RESTORE_INTERRUPTS(oldints);
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294 CYG_TEST_INFO("Dcache off Icache on");
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295 time1();
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296
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297 HAL_DISABLE_INTERRUPTS(oldints);
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298 HAL_DCACHE_PURGE_ALL();
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299 HAL_ICACHE_INVALIDATE_ALL();
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300 HAL_DCACHE_INVALIDATE_ALL();
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301 HAL_ICACHE_ENABLE();
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302 HAL_DCACHE_ENABLE();
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303 HAL_RESTORE_INTERRUPTS(oldints);
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304 CYG_TEST_INFO("Dcache on Icache on");
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305 time1();
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306
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307
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308 HAL_DISABLE_INTERRUPTS(oldints);
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309 HAL_DCACHE_PURGE_ALL();
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310 HAL_ICACHE_INVALIDATE_ALL();
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311 HAL_DCACHE_INVALIDATE_ALL();
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312 HAL_ICACHE_DISABLE();
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313 HAL_DCACHE_DISABLE();
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314 HAL_RESTORE_INTERRUPTS(oldints);
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315 CYG_TEST_INFO("Dcache off Icache off (again)");
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316 time1();
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317
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318 #if defined(HAL_DCACHE_INVALIDATE_ALL) || defined(HAL_ICACHE_INVALIDATE_ALL)
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319 HAL_DISABLE_INTERRUPTS(oldints);
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320 HAL_DCACHE_PURGE_ALL();
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321 HAL_ICACHE_INVALIDATE_ALL();
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322 HAL_DCACHE_INVALIDATE_ALL();
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323 HAL_ICACHE_ENABLE();
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324 HAL_DCACHE_ENABLE();
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325 HAL_RESTORE_INTERRUPTS(oldints);
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326 CYG_TEST_INFO("Dcache on Icache on (again)");
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327 time1();
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328
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329 #if defined(CYGPKG_HAL_MIPS)
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330 // In some architectures, the time taken for the next two tests is
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331 // very long, partly because HAL_XCACHE_INVALIDATE_ALL() is implemented
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332 // with a loop over the cache. Hence these tests take longer than the
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333 // testing infrastructure is prepared to wait. The simplest way to get
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334 // these tests to run quickly is to make them think they are running
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335 // under a simulator.
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336 // If the target actually is a simulator, skip the below - it's very
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337 // slow on the simulator, even with reduced loop counts.
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338 if (cyg_test_is_simulator)
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339 CYG_TEST_PASS_FINISH("End of test");
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340
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341 #if defined(CYGPKG_HAL_MIPS_TX49)
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342 // The TX49 has a large cache, and even with reduced loop count,
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343 // 90+ seconds elapses between each INFO output.
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344 CYG_TEST_PASS_FINISH("End of test");
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345 #endif
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346
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347 cyg_test_is_simulator = 1;
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348 #endif
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349
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350 #ifdef HAL_ICACHE_INVALIDATE_ALL
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351 HAL_DISABLE_INTERRUPTS(oldints);
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352 HAL_DCACHE_PURGE_ALL();
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353 HAL_ICACHE_INVALIDATE_ALL();
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354 HAL_DCACHE_INVALIDATE_ALL();
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355 HAL_ICACHE_ENABLE();
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356 HAL_DCACHE_ENABLE();
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357 HAL_RESTORE_INTERRUPTS(oldints);
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358 CYG_TEST_INFO("Dcache on Icache on: invalidate ICache each time");
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359 time1II();
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360 #endif
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361 #ifdef HAL_DCACHE_INVALIDATE_ALL
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362 HAL_DISABLE_INTERRUPTS(oldints);
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363 HAL_DCACHE_PURGE_ALL();
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364 HAL_ICACHE_INVALIDATE_ALL();
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365 HAL_DCACHE_INVALIDATE_ALL();
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366 HAL_ICACHE_ENABLE();
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367 HAL_DCACHE_ENABLE();
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368 HAL_RESTORE_INTERRUPTS(oldints);
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369 CYG_TEST_INFO("Dcache on Icache on: invalidate DCache (expect bogus times)");
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370 time1DI();
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371 #endif
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372 #endif // either INVALIDATE_ALL macro
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373
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374 #endif // HAL_CACHE_UNIFIED
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375
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376 CYG_TEST_PASS_FINISH("End of test");
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377 }
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378
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379 // -------------------------------------------------------------------------
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380
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381 void kcache2_main( void )
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382 {
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383 CYG_TEST_INIT();
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384
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385 cyg_thread_create(4, entry0 , (cyg_addrword_t)0, "kcache1",
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386 (void *)stack[0], STACKSIZE, &thread[0], &thread_obj[0]);
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387 cyg_thread_resume(thread[0]);
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388
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389 cyg_scheduler_start();
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390 }
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391
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392 // -------------------------------------------------------------------------
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393
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394 externC void
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395 cyg_start( void )
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396 {
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397 kcache2_main();
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398 }
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399
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400 // -------------------------------------------------------------------------
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401
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402 #else // def CYGFUN_KERNEL_API_C
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403 #define N_A_MSG "Kernel C API layer disabled"
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404 #endif // def CYGFUN_KERNEL_API_C
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405 #else // def CYGVAR_KERNEL_COUNTERS_CLOCK
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406 #define N_A_MSG "Kernel real-time clock disabled"
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407 #endif // def CYGVAR_KERNEL_COUNTERS_CLOCK
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408 #else // def HAL_DCACHE_SIZE
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409 #define N_A_MSG "No caches defined"
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410 #endif // def HAL_DCACHE_SIZE
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411
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412 #ifdef N_A_MSG
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413 externC void
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414 cyg_start( void )
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415 {
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416 CYG_TEST_INIT();
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417 CYG_TEST_NA( N_A_MSG );
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418 }
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419 #endif // N_A_MSG
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420
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421 // -------------------------------------------------------------------------
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422 /* EOF kcache1.c */