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annotate packages/hal/powerpc/mpc8xx/current/include/var_cache.h @ 1106:d4e3faad8d75

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author gthomas
date Tue, 15 Jul 2003 00:58:02 +0000
parents 8e23fe1ac05e
children 02b328ea4e09
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1 #ifndef CYGONCE_VAR_CACHE_H
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2 #define CYGONCE_VAR_CACHE_H
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3 //=============================================================================
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4 //
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5 // var_cache.h
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6 //
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7 // Variant HAL cache control API
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8 //
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9 //=============================================================================
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10 //####ECOSGPLCOPYRIGHTBEGIN####
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11 // -------------------------------------------
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12 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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14 // Copyright (C) 2003 Gary Thomas
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later version.
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19 //
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20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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23 // for more details.
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24 //
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25 // You should have received a copy of the GNU General Public License along
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26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 //
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29 // As a special exception, if other files instantiate templates or use macros
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30 // or inline functions from this file, or you compile this file and link it
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31 // with other works to produce a work based on this file, this file does not
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32 // by itself cause the resulting work to be covered by the GNU General Public
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33 // License. However the source code for this file must still be made available
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34 // in accordance with section (3) of the GNU General Public License.
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35 //
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36 // This exception does not invalidate any other reasons why a work based on
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37 // this file might be covered by the GNU General Public License.
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38 //
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39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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40 // at http://sources.redhat.com/ecos/ecos-license/
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41 // -------------------------------------------
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42 //####ECOSGPLCOPYRIGHTEND####
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43 //=============================================================================
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44 //#####DESCRIPTIONBEGIN####
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45 //
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46 // Author(s): nickg
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47 // Contributors:nickg, jskov
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48 // Date: 2000-04-02
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49 // Purpose: Variant cache control API
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50 // Description: The macros defined here provide the HAL APIs for handling
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51 // cache control operations on the MPC8xx variant CPUs.
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52 // Usage: Is included via the architecture cache header:
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53 // #include <cyg/hal/hal_cache.h>
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54 // ...
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55 //
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56 //####DESCRIPTIONEND####
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57 //
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58 //=============================================================================
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59
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60 #include <pkgconf/hal.h>
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61 #include <cyg/infra/cyg_type.h>
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62
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63 #include <cyg/hal/ppc_regs.h>
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64
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65 #include <cyg/hal/plf_cache.h>
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66
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67
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68 //-----------------------------------------------------------------------------
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69 // Cache dimensions - these vary between the 8xx sub-models
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70
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71 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_862P)
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72 // Data cache
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73 #define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes
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74 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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75 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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76
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77 // Instruction cache
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78 #define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
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79 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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80 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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81 #endif // defined(CYGHWR_HAL_POWERPC_MPC862P)
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82
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83 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \
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84 defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \
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85 defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \
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86 defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \
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87 defined(CYGHWR_HAL_POWERPC_MPC8XX_852T)
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88 // Data cache
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89 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
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90 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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91 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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92
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93 // Instruction cache
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94 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
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95 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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96 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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97 #endif // defined(CYGHWR_HAL_POWERPC_MPC860)
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98
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99 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || \
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100 defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
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101 // Data cache
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102 #define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
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103 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
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104 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
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105
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106 // Instruction cache
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107 #define HAL_ICACHE_SIZE 2048 // Size of cache in bytes
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108 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
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109 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
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110 #endif // defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
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111
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112 #ifndef HAL_ICACHE_SIZE
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113 #error Missing cache definitions for this processor?
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114 #endif
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115
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116 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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117 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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118
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119 //-----------------------------------------------------------------------------
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120 // Global control of data cache
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121
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122 // Enable the data cache
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123 #define HAL_DCACHE_ENABLE() \
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124 asm volatile ("sync;" \
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125 "mtspr %0, %1;" \
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126 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE))
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127
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128 // Disable the data cache
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129 #define HAL_DCACHE_DISABLE() \
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130 asm volatile ("sync;" \
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131 "mtspr %0, %1;" \
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132 : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD))
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133
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134 // Invalidate the entire cache
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135 // Note: Any locked lines will not be invalidated.
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136 #define HAL_DCACHE_INVALIDATE_ALL() \
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137 asm volatile ("sync;" \
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138 "mtspr %0, %1;" \
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139 : : "I" (CYGARC_REG_DC_CST), \
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140 "r" (CYGARC_REG_DC_CMD_IA))
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141
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142 // Synchronize the contents of the cache with memory.
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143 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
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144 // Note: the data cache flush seems to be broken on this chip :-(
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145 #define HAL_DCACHE_SYNC() \
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146 CYG_MACRO_START \
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147 cyg_int32 i; \
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148 cyg_uint32 *__base = (cyg_uint32 *) (0); \
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149 for(i=0;i< (2 * HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){ \
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150 asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0"); \
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151 } \
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152 CYG_MACRO_END
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153 #else
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154 #define HAL_DCACHE_SYNC() \
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155 CYG_MACRO_START \
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156 cyg_int32 i; \
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157 for (i = 0; i < HAL_DCACHE_SETS; i++){ \
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158 asm volatile ("sync;" \
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159 "mtspr %0, %2;" \
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160 "mtspr %1, %4;" \
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161 "mtspr %0, %3;" \
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162 "mtspr %1, %4;" \
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163 : /* no output */ \
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164 : /* %0 */ "I" (CYGARC_REG_DC_ADR), \
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165 /* %1 */ "I" (CYGARC_REG_DC_CST), \
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166 /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0 \
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167 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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168 /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1 \
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169 |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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170 /* %4 */ "r" (CYGARC_REG_DC_CMD_FL)); \
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171 } \
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172 CYG_MACRO_END
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173 #endif
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174
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175 // Query the state of the data cache
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176 #define HAL_DCACHE_IS_ENABLED(_state_) \
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177 asm volatile ("mfspr %0, %1;" \
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178 "rlwinm %0,%0,1,31,31;" \
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179 : "=r" (_state_) : "I" (CYGARC_REG_DC_CST))
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180
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181 // Set the data cache refill burst size
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182 //#define HAL_DCACHE_BURST_SIZE(_size_)
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183
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184 // Set the data cache write mode
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185 #define HAL_DCACHE_WRITE_MODE( _mode_ ) \
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186 CYG_MACRO_START \
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187 if (_mode_ == HAL_DCACHE_WRITETHRU_MODE) { \
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188 asm volatile ("sync;" \
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189 "mtspr %0, %1;" \
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190 : : "I" (CYGARC_REG_DC_CST), \
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191 "r" (CYGARC_REG_DC_CMD_SW)); \
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192 } \
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193 if (_mode_ == HAL_DCACHE_WRITEBACK_MODE) { \
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194 asm volatile ("sync;" \
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195 "mtspr %0, %1;" \
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196 : : "I" (CYGARC_REG_DC_CST), \
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197 "r" (CYGARC_REG_DC_CMD_CW)); \
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198 } \
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199 CYG_MACRO_END
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200
419
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201 #define HAL_DCACHE_WRITETHRU_MODE 0
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202 #define HAL_DCACHE_WRITEBACK_MODE 1
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203
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204
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205 // Load the contents of the given address range into the data cache
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206 // and then lock the cache so that it stays there.
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207
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208 // Restrictions: This implementation only allows a single area to be
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209 // locked at any one time. This area must be 2kB or less in size.
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210
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211 // Implementation: Flush entire cache, then invalidate it. This
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212 // ensures that the fetched data go into way0.
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213
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214 #define HAL_DCACHE_LOCK(_base_, _size_) \
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215 CYG_MACRO_START \
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216 cyg_int32 __scratch; \
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217 cyg_uint32 __base = (cyg_uint32)(_base_); \
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218 cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS); \
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219 cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE); \
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220 HAL_DCACHE_DISABLE(); \
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221 HAL_DCACHE_SYNC (); \
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222 HAL_DCACHE_INVALIDATE_ALL (); \
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223 HAL_DCACHE_ENABLE(); \
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224 do { \
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225 asm volatile ("lbz %0,0(%1);" \
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226 "sync;" \
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227 "mtspr %2, %4;" \
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228 "mtspr %3, %5;" \
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229 : /* %0 */ "=&r" (__scratch) \
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230 : /* %1 */ "b" (__base), \
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231 /* %2 */ "I" (CYGARC_REG_DC_ADR), \
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232 /* %3 */ "I" (CYGARC_REG_DC_CST), \
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233 /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0 \
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234 |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \
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235 /* %5 */ "r" (CYGARC_REG_DC_CMD_LL)); \
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236 __l++; \
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237 __base += HAL_DCACHE_LINE_SIZE; \
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238 } while (__count--); \
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239 CYG_MACRO_END
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240
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241
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242 // Undo a previous lock operation
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243
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244 // Implementation: Unlocks entire cache.
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245
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246 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
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247 HAL_DCACHE_UNLOCK_ALL()
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248
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249
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250 // Unlock entire cache
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251 #define HAL_DCACHE_UNLOCK_ALL() \
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252 CYG_MACRO_START \
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253 asm volatile ("sync;" \
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254 "mtspr %0, %1;" \
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255 : : "I" (CYGARC_REG_DC_CST), \
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256 "r" (CYGARC_REG_DC_CMD_UA)); \
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257 CYG_MACRO_END
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258
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259
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260
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261 //-----------------------------------------------------------------------------
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262 // Data cache line control
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263
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264 // Allocate cache lines for the given address range without reading its
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265 // contents from memory.
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266 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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267
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268 // Write dirty cache lines to memory and invalidate the cache entries
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269 // for the given address range.
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270 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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271 CYG_MACRO_START \
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272 cyg_uint32 __base = (cyg_uint32) (_base_); \
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273 cyg_int32 __size = (cyg_int32) (_size_); \
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274 while (__size > 0) { \
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275 asm volatile ("dcbf 0,%0;sync;" : : "r" (__base)); \
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276 __base += HAL_DCACHE_LINE_SIZE; \
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277 __size -= HAL_DCACHE_LINE_SIZE; \
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278 } \
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279 CYG_MACRO_END
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280
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281 // Invalidate cache lines in the given range without writing to memory.
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282 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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283 CYG_MACRO_START \
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284 cyg_uint32 __base = (cyg_uint32) (_base_); \
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285 cyg_int32 __size = (cyg_int32) (_size_); \
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286 while (__size > 0) { \
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287 asm volatile ("dcbi 0,%0;sync;" : : "r" (__base)); \
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288 __base += HAL_DCACHE_LINE_SIZE; \
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289 __size -= HAL_DCACHE_LINE_SIZE; \
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290 } \
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291 CYG_MACRO_END
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292
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293 // Write dirty cache lines to memory for the given address range.
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294 #define HAL_DCACHE_STORE( _base_ , _size_ ) \
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295 CYG_MACRO_START \
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296 cyg_uint32 __base = (cyg_uint32) (_base_); \
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297 cyg_int32 __size = (cyg_int32) (_size_); \
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298 while (__size > 0) { \
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299 asm volatile ("dcbst 0,%0;sync;" : : "r" (__base)); \
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300 __base += HAL_DCACHE_LINE_SIZE; \
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301 __size -= HAL_DCACHE_LINE_SIZE; \
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302 } \
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303 CYG_MACRO_END
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304
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305 // Preread the given range into the cache with the intention of reading
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306 // from it later.
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307 #define HAL_DCACHE_READ_HINT( _base_ , _size_ ) \
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308 CYG_MACRO_START \
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309 cyg_uint32 __base = (cyg_uint32) (_base_); \
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310 cyg_int32 __size = (cyg_int32) (_size_); \
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311 while (__size > 0) { \
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312 asm volatile ("dcbt 0,%0;" : : "r" (__base)); \
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313 __base += HAL_DCACHE_LINE_SIZE; \
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314 __size -= HAL_DCACHE_LINE_SIZE; \
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315 } \
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316 CYG_MACRO_END
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317
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318 // Preread the given range into the cache with the intention of writing
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319 // to it later.
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320 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) \
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321 CYG_MACRO_START \
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322 cyg_uint32 __base = (cyg_uint32) (_base_); \
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323 cyg_int32 __size = (cyg_int32) (_size_); \
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324 while (__size > 0) { \
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325 asm volatile ("dcbtst 0,%0;" : : "r" (__base)); \
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326 __base += HAL_DCACHE_LINE_SIZE; \
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327 __size -= HAL_DCACHE_LINE_SIZE; \
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328 } \
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329 CYG_MACRO_END
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330
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331 // Allocate and zero the cache lines associated with the given range.
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332 #define HAL_DCACHE_ZERO( _base_ , _size_ ) \
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333 CYG_MACRO_START \
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334 cyg_uint32 __base = (cyg_uint32) (_base_); \
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335 cyg_int32 __size = (cyg_int32) (_size_); \
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336 while (__size > 0) { \
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337 asm volatile ("dcbz 0,%0;" : : "r" (__base)); \
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338 __base += HAL_DCACHE_LINE_SIZE; \
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339 __size -= HAL_DCACHE_LINE_SIZE; \
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340 } \
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341 CYG_MACRO_END
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342
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343 //-----------------------------------------------------------------------------
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344 // Global control of Instruction cache
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345
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346 // Enable the instruction cache
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347 #define HAL_ICACHE_ENABLE() \
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348 asm volatile ("isync;" \
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349 "mtspr %0, %1;" \
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350 "isync" \
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351 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE))
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352
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353 // Disable the instruction cache
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354 #define HAL_ICACHE_DISABLE() \
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355 asm volatile ("isync;" \
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356 "mtspr %0, %1;" \
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357 "isync" \
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358 : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD))
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359
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360 // Invalidate the entire cache
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361 #define HAL_ICACHE_INVALIDATE_ALL() \
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362 asm volatile ("isync;" \
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363 "mtspr %0, %1;" \
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364 "isync" \
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365 : : "I" (CYGARC_REG_IC_CST), \
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366 "r" (CYGARC_REG_IC_CMD_IA))
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367
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368 // Synchronize the contents of the cache with memory.
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369 #define HAL_ICACHE_SYNC() \
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370 HAL_ICACHE_INVALIDATE_ALL()
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371
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372 // Query the state of the instruction cache
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373 #define HAL_ICACHE_IS_ENABLED(_state_) \
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374 asm volatile ("mfspr %0, %1;" \
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375 "rlwinm %0,%0,1,31,31;" \
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376 : "=r" (_state_) : "I" (CYGARC_REG_IC_CST))
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377
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378 // Set the instruction cache refill burst size
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379 //#define HAL_ICACHE_BURST_SIZE(_size_)
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380
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381
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382 // Load the contents of the given address range into the instruction cache
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383 // and then lock the cache so that it stays there.
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384
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385 // Restrictions: This implementation only allows a single area to be
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386 // locked at any one time. This area must be 2kB or less in size.
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387
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388 // Implementation: Flush entire cache, then invalidate it. This
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389 // ensures that the fetched data go into way0.
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390
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391 #define HAL_ICACHE_LOCK(_base_, _size_) \
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392 CYG_MACRO_START \
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393 unsigned long __base = \
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394 ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1); \
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395 int __count = ((_size_) / HAL_ICACHE_LINE_SIZE); \
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396 do { \
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397 asm volatile ("mtspr %0, %2;" \
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398 "mtspr %1, %3;" \
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399 "isync;" \
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400 : /* no output */ \
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401 : /* %0 */ "I" (CYGARC_REG_IC_ADR), \
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402 /* %1 */ "I" (CYGARC_REG_IC_CST), \
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403 /* %2 */ "r" (__base), \
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404 /* %3 */ "r" (CYGARC_REG_IC_CMD_LL)); \
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405 __base += HAL_ICACHE_LINE_SIZE; \
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406 } while (__count--); \
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407 CYG_MACRO_END
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408
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409 // Undo a previous lock operation
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410
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411 // Implementation: Unlocks entire cache.
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412 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
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413 HAL_ICACHE_UNLOCK_ALL()
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414
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415 // Unlock entire cache
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416 #define HAL_ICACHE_UNLOCK_ALL() \
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417 CYG_MACRO_START \
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418 asm volatile ("sync;" \
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419 "mtspr %0, %1;" \
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420 : : "I" (CYGARC_REG_IC_CST), \
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421 "r" (CYGARC_REG_IC_CMD_UA)); \
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422 CYG_MACRO_END
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423
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424 //-----------------------------------------------------------------------------
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425 // Instruction cache line control
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426
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427 // Invalidate cache lines in the given range without writing to memory.
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428 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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429
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430 //-----------------------------------------------------------------------------
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431 #endif // ifndef CYGONCE_VAR_CACHE_H
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432 // End of var_cache.h