flash_v2: packages/hal/mips/arch/current/include/hal

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 1656:ea74d0ea9eb1

* include/hal_cache.h: Changed the calculation of _IWAY and _DWAY for the case where HAL_MIPS_CACHE_INSN_USES_LSB is set to only affect the LSBs in the CACHE instruction offset field. #define MIPS cache ops and use them instead of constants in the HAL_?CACHE_* macros below.

author	jlarmour
date	Thu, 27 May 2004 06:26:53 +0000
parents	bac0bf105669
children

rev	line source
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1 #ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 #define CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	6 // hal_cache.h
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	7 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	8 // HAL cache control API
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 //=============================================================================
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	11 //####ECOSGPLCOPYRIGHTBEGIN####
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	12 // -------------------------------------------
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	13 // This file is part of eCos, the Embedded Configurable Operating System.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	15 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	16 // eCos is free software; you can redistribute it and/or modify it under
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	17 // the terms of the GNU General Public License as published by the Free
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	18 // Software Foundation; either version 2 or (at your option) any later version.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	19 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	23 // for more details.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	24 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	25 // You should have received a copy of the GNU General Public License along
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	26 // with eCos; if not, write to the Free Software Foundation, Inc.,
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	28 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	29 // As a special exception, if other files instantiate templates or use macros
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	30 // or inline functions from this file, or you compile this file and link it
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	31 // with other works to produce a work based on this file, this file does not
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	32 // by itself cause the resulting work to be covered by the GNU General Public
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	33 // License. However the source code for this file must still be made available
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	34 // in accordance with section (3) of the GNU General Public License.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	35 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	36 // This exception does not invalidate any other reasons why a work based on
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	37 // this file might be covered by the GNU General Public License.
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	38 //
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
210 d2c90368aeef Merge from eCos master repository on 2002-05-23-21:39:14-BST jlarmour parents: 208 diff changeset	40 // at http://sources.redhat.com/ecos/ecos-license/
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	41 // -------------------------------------------
e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	42 //####ECOSGPLCOPYRIGHTEND####
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	43 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	44 //#####DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	45 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	46 // Author(s): nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	47 // Contributors: nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	48 // Date: 1998-02-17
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	49 // Purpose: Cache control API
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	50 // Description: The macros defined here provide the HAL APIs for handling
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	51 // cache control operations.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	52 // Usage:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	53 // #include <cyg/hal/hal_cache.h>
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	54 // ...
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	55 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	56 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	57 //####DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	58 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	59 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	60
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	61 #include <pkgconf/hal.h>
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	62 #include <cyg/infra/cyg_type.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	63
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	64 #include <cyg/hal/var_cache.h>
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	65
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	66 // Use this macro to allow the assembler to accept "cache" instructions,
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	67 // which are MIPS ISA 3. This is useful if someone is compiling
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	68 // with -mips2, but the architecture is really MIPS ISA 3.
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	69
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	70 #define _hal_asm_mips_cpp_stringize( _x_ ) #_x_
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	71 #define _HAL_ASM_SET_MIPS_ISA( _isal_ ) asm volatile ( \
121 6bd9d475ed4b Merge from eCos master repository on 2000-09-04-20:50:20-BST jlarmour parents: 92 diff changeset	72 ".set mips" _hal_asm_mips_cpp_stringize(_isal_) )
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	73
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	74
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	75 //=============================================================================
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	76 // Default Implementation. This uses the standard MIPS CP0 registers and
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	77 // cache instructions. Note that not all variants will have all of the
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	78 // functionality defined here.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	79
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	80 //-----------------------------------------------------------------------------
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	81 // Cache dimensions.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	82 // These really should be defined in var_cache.h. If they are not, then provide
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	83 // a set of numbers that are typical of many variants.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	84
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	85 #ifndef HAL_DCACHE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	86
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	87 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	88 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	89 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	90 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	91
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	92 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	93 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	94 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	95 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	96
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	97 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	98 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	99
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	100 #endif
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	101
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	102 // Defines for various R4000+ MIPS cache operations
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	103 // this is a 5 bit field with bits 4-2 defining the operation
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	104 // and bits 1-0 defining which cache is being operated on
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	105 #define HAL_MIPS_CACHE_INDEX_INVALIDATE_I 0x00 /* 0 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	106 #define HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_D 0x01 /* 0 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	107 #define HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_S 0x03 /* 0 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	108 #define HAL_MIPS_CACHE_INDEX_LOAD_TAG_I 0x04 /* 1 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	109 #define HAL_MIPS_CACHE_INDEX_LOAD_TAG_D 0x05 /* 1 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	110 #define HAL_MIPS_CACHE_INDEX_LOAD_TAG_S 0x07 /* 1 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	111 #define HAL_MIPS_CACHE_INDEX_STORE_TAG_I 0x08 /* 2 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	112 #define HAL_MIPS_CACHE_INDEX_STORE_TAG_D 0x09 /* 2 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	113 #define HAL_MIPS_CACHE_INDEX_STORE_TAG_S 0x0b /* 2 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	114 #define HAL_MIPS_CACHE_HIT_INVALIDATE_I 0x10 /* 4 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	115 #define HAL_MIPS_CACHE_HIT_INVALIDATE_D 0x11 /* 4 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	116 #define HAL_MIPS_CACHE_HIT_INVALIDATE_S 0x13 /* 4 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	117 #define HAL_MIPS_CACHE_FILL_I 0x14 /* 5 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	118 #define HAL_MIPS_CACHE_HIT_WRITEBACK_INV_D 0x15 /* 5 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	119 #define HAL_MIPS_CACHE_HIT_WRITEBACK_INV_S 0x17 /* 5 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	120
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	121 // there seems to be different uses for operation
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	122 // code 6 depending on CPU
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	123 #define HAL_MIPS_CACHE_HIT_WRITEBACK_D 0x19 /* 6 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	124
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	125 #define HAL_MIPS_CACHE_INDEX_LOAD_DATA_I 0x18 /* 6 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	126 #define HAL_MIPS_CACHE_INDEX_LOAD_DATA_D 0x19 /* 6 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	127 #define HAL_MIPS_CACHE_INDEX_LOAD_DATA_S 0x1b /* 6 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	128
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	129 // there seems to be different uses for operation
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	130 // code 7 depending on CPU
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	131 #define HAL_MIPS_CACHE_FETCH_AND_LOCK_I 0x1c /* 7 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	132 #define HAL_MIPS_CACHE_FETCH_AND_LOCK_D 0x1d /* 7 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	133
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	134 #define HAL_MIPS_CACHE_INDEX_STORE_DATA_I 0x1c /* 7 0 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	135 #define HAL_MIPS_CACHE_INDEX_STORE_DATA_D 0x1d /* 7 1 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	136 #define HAL_MIPS_CACHE_INDEX_STORE_DATA_S 0x1f /* 7 3 */
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	137
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	138
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	139 //-----------------------------------------------------------------------------
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	140 // Cache instruction uses LSBs or MSBs (depending on the
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	141 // implementation) of the virtual address to specify which WAY to
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	142 // affect. The _ALL_WAYS macro defines the necessary cache instructions
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	143 // to affect all ways.
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	144
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	145 #ifdef HAL_MIPS_CACHE_INSN_USES_LSB
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	146 # define _IWAY(_n_) (_n_)
ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	147 # define _DWAY(_n_) (_n_)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	148 #else
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	149 # define _IWAY(_n_) ((_n_)*HAL_ICACHE_SIZE/HAL_ICACHE_WAYS)
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	150 # define _DWAY(_n_) ((_n_)*HAL_DCACHE_SIZE/HAL_DCACHE_WAYS)
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	151 #endif
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	152
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	153 #if (HAL_DCACHE_WAYS == 1)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	154 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	155 asm volatile ("cache %0,0(%1);" \
124 0ec04793409a Merge from eCos master repository on 2000-09-11-03:00:13-BST jlarmour parents: 121 diff changeset	156 : : "I" ((_cmd_) \| 1), "r"(_addr_) )
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	157 #elif (HAL_DCACHE_WAYS == 2)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	158 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	159 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	160 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	161 : : "I" ((_cmd_) \| 1), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	162 "I" (_DWAY(1)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	163 #elif (HAL_DCACHE_WAYS == 4)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	164 #define _HAL_ASM_DCACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	165 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	166 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	167 "cache %0,%3(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	168 "cache %0,%4(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	169 : : "I" ((_cmd_) \| 1), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	170 "I" (_DWAY(1)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	171 "I" (_DWAY(2)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	172 "I" (_DWAY(3)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	173 #else
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	174 # error "Unsupported number of ways"
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	175 #endif
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	176
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	177 #if (HAL_ICACHE_WAYS == 1)
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	178 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	179 asm volatile ("cache %0,0(%1);" \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	180 : : "I" (_cmd_), "r"(_addr_) )
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	181 #elif (HAL_ICACHE_WAYS == 2)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	182 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	183 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	184 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	185 : : "I" (_cmd_), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	186 "I" (_IWAY(1)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	187 #elif (HAL_ICACHE_WAYS == 4)
143 6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	188 #define _HAL_ASM_ICACHE_ALL_WAYS( _cmd_ , _addr_ ) \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	189 asm volatile ("cache %0,0(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	190 "cache %0,%2(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	191 "cache %0,%3(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	192 "cache %0,%4(%1);" \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	193 : : "I" (_cmd_), "r"(_addr_), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	194 "I" (_IWAY(1)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	195 "I" (_IWAY(2)), \
6b5f480c6929 Merge from eCos master repository on 2000-12-08-02:09:36-GMT jlarmour parents: 124 diff changeset	196 "I" (_IWAY(3)))
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	197 #else
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	198 # error "Unsupported number of ways"
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	199 #endif
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	200
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	201 //-----------------------------------------------------------------------------
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	202 // Address adjustment.
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	203 // Given an address and a size, these macros return the first
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	204 // cacheline containing the requested range and a terminating address.
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	205
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	206 #define HAL_DCACHE_START_ADDRESS(_addr_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	207 (((CYG_ADDRESS)(_addr_)) & ~(HAL_DCACHE_LINE_SIZE-1))
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	208
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	209 #define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	210 ((CYG_ADDRESS)((_addr_) + (_asize_)))
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	211
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	212 #define HAL_ICACHE_START_ADDRESS(_addr_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	213 (((CYG_ADDRESS)(_addr_)) & ~(HAL_ICACHE_LINE_SIZE-1))
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	214
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	215 #define HAL_ICACHE_END_ADDRESS(_addr_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	216 ((CYG_ADDRESS)((_addr_) + (_asize_)))
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	217
208 e0c0827131d1 Merge from eCos master repository on 2002-05-20-20:11:54-BST jlarmour parents: 143 diff changeset	218 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	219 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	220
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	221 // Enable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	222 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	223 #ifndef HAL_DCACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	224 #define HAL_DCACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	225 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	226
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	227 // Disable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	228 #ifndef HAL_DCACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	229 #define HAL_DCACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	230 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	231
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	232 #ifndef HAL_DCACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	233 #define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	234 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	235
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	236 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	237 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	238 // is not quite what we want, but there is no index-invalidate operation
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	239 // available.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	240 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	241 #define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	242 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	243
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	244 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	245 // This uses the index-writeback-invalidate operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	246 #ifndef HAL_DCACHE_SYNC_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	247 #define HAL_DCACHE_SYNC() \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	248 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	249 register CYG_ADDRESS _baddr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	250 register CYG_ADDRESS _addr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	251 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	252 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	253 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	254 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_INDEX_WRITEBACK_INV_D, _addr_); } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	255 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	256 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	257 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	258
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	259 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	260 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	261
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	262 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	263 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	264
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	265 //#define HAL_DCACHE_WRITETHRU_MODE 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	266 //#define HAL_DCACHE_WRITEBACK_MODE 1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	267
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	268 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	269 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	270 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	271 #ifndef HAL_DCACHE_LOCK_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	272 #define HAL_DCACHE_LOCK(_base_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	273 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	274 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	275 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	276 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	277 HAL_DCACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	278 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	279 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	280 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	281 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_FETCH_AND_LOCK_D, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	282 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	283 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	284 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	285 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	286
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	287 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	288 // Do this by flushing the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	289 #ifndef HAL_DCACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	290 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	291 HAL_DCACHE_FLUSH( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	292 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	293
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	294 // Unlock entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	295 #ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	296 #define HAL_DCACHE_UNLOCK_ALL() \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	297 HAL_DCACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	298 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	299
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	300 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	301 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	302
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	303 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	304 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	305 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	306
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	307 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	308 // for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	309 // This uses the hit-writeback-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	310 #ifndef HAL_DCACHE_FLUSH_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	311 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	312 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	313 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	314 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	315 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	316 HAL_DCACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	317 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	318 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	319 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	320 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_WRITEBACK_INV_D, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	321 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	322 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	323 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	324 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	325
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	326 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	327 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	328 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	329 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	330 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	331 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	332 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	333 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	334 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	335 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_INVALIDATE_D, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	336 _HAL_ASM_SET_MIPS_ISA(0); \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	337 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	338 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	339
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	340 // Write dirty cache lines to memory for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	341 // This uses the hit-writeback cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	342 #ifndef HAL_DCACHE_STORE_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	343 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	344 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	345 register CYG_ADDRESS _addr_ = HAL_DCACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	346 register CYG_ADDRESS _eaddr_ = HAL_DCACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	347 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	348 HAL_DCACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	349 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	350 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	351 for( ; _addr_ < _eaddr_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	352 { _HAL_ASM_DCACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_WRITEBACK_D, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	353 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	354 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	355 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	356 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	357
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	358 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	359 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	360 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	361
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	362 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	363 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	364 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	365
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	366 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	367 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	368
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	369 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	370 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	371
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	372 // Enable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	373 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	374 #ifndef HAL_ICACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	375 #define HAL_ICACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	376 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	377
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	378 // Disable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	379 #ifndef HAL_ICACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	380 #define HAL_ICACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	381 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	382
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	383 #ifndef HAL_ICACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	384 #define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	385 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	386
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	387 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	388 // This uses the index-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	389 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	390 #define HAL_ICACHE_INVALIDATE_ALL() \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	391 CYG_MACRO_START \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	392 register CYG_ADDRESS _baddr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	393 register CYG_ADDRESS _addr_ = 0x80000000; \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	394 _HAL_ASM_SET_MIPS_ISA(3); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	395 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	396 { _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_INDEX_INVALIDATE_I, _addr_); } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	397 _HAL_ASM_SET_MIPS_ISA(0); \
08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	398 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	399 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	400
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	401 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	402 // Simply force the cache to reload.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	403 #ifndef HAL_ICACHE_SYNC_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	404 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	405 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	406
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	407 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	408 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	409
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	410 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	411 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	412 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	413 #ifndef HAL_ICACHE_LOCK_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	414 #define HAL_ICACHE_LOCK(_base_, _asize_) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	415 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	416 register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	417 register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	418 register CYG_WORD _state_; \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	419 HAL_ICACHE_IS_ENABLED( _state_ ); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	420 if( _state_ ) { \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	421 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	422 for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	423 { _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_FETCH_AND_LOCK_I, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	424 _HAL_ASM_SET_MIPS_ISA(0); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	425 } \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	426 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	427 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	428
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	429 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	430 // Do this by invalidating the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	431 #ifndef HAL_ICACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	432 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	433 HAL_ICACHE_INVALIDATE( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	434 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	435
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	436 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	437 //#define HAL_ICACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	438
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	439 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	440 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	441
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	442 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	443 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	444 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	445 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	446 CYG_MACRO_START \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	447 register CYG_ADDRESS _addr_ = HAL_ICACHE_START_ADDRESS(_base_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	448 register CYG_ADDRESS _eaddr_ = HAL_ICACHE_END_ADDRESS(_base_, _asize_); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	449 _HAL_ASM_SET_MIPS_ISA(3); \
bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	450 for( ; _addr_ < _eaddr_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
1656 ea74d0ea9eb1 * include/hal_cache.h: Changed the calculation of _IWAY and _DWAY jlarmour parents: 464 diff changeset	451 { _HAL_ASM_ICACHE_ALL_WAYS(HAL_MIPS_CACHE_HIT_INVALIDATE_I, _addr_); } \
464 bac0bf105669 Fix cache macros, which could go wrong if the base address was not on bartv parents: 210 diff changeset	452 _HAL_ASM_SET_MIPS_ISA(0); \
92 08ffab08d2ee Merge from eCos master repository on 2000-05-26-07:47:03-BST jlarmour parents: 76 diff changeset	453 CYG_MACRO_END
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	454 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	455
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	456 //-----------------------------------------------------------------------------
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	457 // Check that a supported configuration has actually defined some macros.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	458
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	459 #ifndef HAL_DCACHE_ENABLE
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	460
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	461 #error Unsupported MIPS configuration
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	462
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	463 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	464
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	465 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	466 #endif // ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	467 // End of hal_cache.h

Mercurial > flash_v2

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 1656:ea74d0ea9eb1