Mercurial > flash_v2
annotate packages/kernel/current/src/intr/intr.cxx @ 130:eb9fd8c04db3 ecos-sw-2000-10-23
Merge from eCos master repository on 2000-10-23-17:01:37-BST
| author | jlarmour |
|---|---|
| date | Mon, 23 Oct 2000 17:10:57 +0000 |
| parents | 0c2b7be0d798 |
| children | 38892b97b685 |
| rev | line source |
|---|---|
| 0 | 1 //========================================================================== |
| 2 // | |
| 2 | 3 // intr/intr.cxx |
| 0 | 4 // |
| 2 | 5 // Interrupt class implementations |
| 0 | 6 // |
| 7 //========================================================================== | |
| 8 //####COPYRIGHTBEGIN#### | |
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9 // |
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10 // ------------------------------------------- |
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11 // The contents of this file are subject to the Red Hat eCos Public License |
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12 // Version 1.1 (the "License"); you may not use this file except in |
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13 // compliance with the License. You may obtain a copy of the License at |
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14 // http://www.redhat.com/ |
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15 // |
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16 // Software distributed under the License is distributed on an "AS IS" |
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17 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the |
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18 // License for the specific language governing rights and limitations under |
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19 // the License. |
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20 // |
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21 // The Original Code is eCos - Embedded Configurable Operating System, |
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22 // released September 30, 1998. |
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23 // |
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24 // The Initial Developer of the Original Code is Red Hat. |
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25 // Portions created by Red Hat are |
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26 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. |
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27 // All Rights Reserved. |
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28 // ------------------------------------------- |
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29 // |
| 0 | 30 //####COPYRIGHTEND#### |
| 31 //========================================================================== | |
| 32 //#####DESCRIPTIONBEGIN#### | |
| 33 // | |
| 2 | 34 // Author(s): nickg |
| 35 // Contributors: nickg | |
| 36 // Date: 1999-02-17 | |
| 37 // Purpose: Interrupt class implementation | |
| 38 // Description: This file contains the definitions of the interrupt | |
| 39 // class. | |
| 0 | 40 // |
| 41 //####DESCRIPTIONEND#### | |
| 42 // | |
| 43 //========================================================================== | |
| 44 | |
| 45 #include <pkgconf/kernel.h> | |
| 46 | |
| 47 #include <cyg/kernel/ktypes.h> // base kernel types | |
| 48 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 49 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 50 #include <cyg/kernel/instrmnt.h> // instrumentation | |
| 51 | |
| 52 #include <cyg/kernel/intr.hxx> // our header | |
| 53 | |
| 54 #include <cyg/kernel/sched.hxx> // scheduler | |
| 55 | |
| 56 #include <cyg/kernel/sched.inl> | |
| 57 | |
| 58 // ------------------------------------------------------------------------- | |
| 2 | 59 // Statics |
| 60 | |
| 61 // Interrupt disable counter. Note that this is initialized to 1 since | |
| 62 // enable_interrupts() is called in Cyg_Scheduler::start(). | |
| 63 | |
| 64 cyg_int32 Cyg_Interrupt::disable_counter = 1; | |
| 65 | |
| 66 // ------------------------------------------------------------------------- | |
| 0 | 67 |
| 68 Cyg_Interrupt::Cyg_Interrupt( | |
| 69 cyg_vector vec, // Vector to attach to | |
| 70 cyg_priority pri, // Queue priority | |
| 71 CYG_ADDRWORD d, // Data pointer | |
| 72 cyg_ISR *ir, // Interrupt Service Routine | |
| 73 cyg_DSR *dr // Deferred Service Routine | |
| 74 ) | |
| 75 { | |
| 2 | 76 CYG_REPORT_FUNCTION(); |
| 77 CYG_REPORT_FUNCARG5("vector=%d, priority=%d, data=%08x, isr=%08x, " | |
| 78 "dsr=%08x", vec, pri, d, ir, dr); | |
| 79 | |
| 0 | 80 vector = vec; |
| 81 priority = pri; | |
| 82 isr = ir; | |
| 83 dsr = dr; | |
| 84 data = d; | |
| 85 | |
| 86 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 87 | |
| 88 dsr_count = 0; | |
| 89 next_dsr = NULL; | |
| 90 | |
| 91 #endif | |
| 92 | |
| 93 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 94 | |
| 95 next = NULL; | |
| 96 | |
| 97 #endif | |
| 2 | 98 |
| 99 CYG_REPORT_RETURN(); | |
| 0 | 100 |
| 101 }; | |
| 102 | |
| 103 // ------------------------------------------------------------------------- | |
| 104 | |
| 105 Cyg_Interrupt::~Cyg_Interrupt() | |
| 106 { | |
| 2 | 107 CYG_REPORT_FUNCTION(); |
| 0 | 108 detach(); |
| 2 | 109 CYG_REPORT_RETURN(); |
| 0 | 110 }; |
| 111 | |
| 112 // ------------------------------------------------------------------------- | |
| 113 // DSR handling statics: | |
| 114 | |
| 115 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 116 | |
| 2 | 117 Cyg_Interrupt * |
| 118 Cyg_Interrupt::dsr_table[CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]; | |
| 0 | 119 |
| 120 cyg_ucount32 Cyg_Interrupt::dsr_table_head = 0; | |
| 121 | |
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122 volatile cyg_ucount32 Cyg_Interrupt::dsr_table_tail = 0; |
| 0 | 123 |
| 124 #endif | |
| 125 | |
| 126 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 127 | |
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128 Cyg_Interrupt* volatile Cyg_Interrupt::dsr_list = NULL; |
| 0 | 129 |
| 130 #endif | |
| 131 | |
| 132 // ------------------------------------------------------------------------- | |
| 133 // Call any pending DSRs | |
| 134 | |
| 2 | 135 void |
| 136 Cyg_Interrupt::call_pending_DSRs_inner(void) | |
| 0 | 137 { |
| 138 // CYG_REPORT_FUNCTION(); | |
| 139 | |
| 140 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 141 | |
| 142 while( dsr_table_head != dsr_table_tail ) | |
| 143 { | |
| 144 Cyg_Interrupt *intr = dsr_table[dsr_table_head]; | |
| 145 | |
| 146 dsr_table_head++; | |
| 147 if( dsr_table_head >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) | |
| 148 dsr_table_head = 0; | |
| 149 | |
| 150 CYG_INSTRUMENT_INTR(CALL_DSR, intr->vector, 0); | |
| 151 | |
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152 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
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153 |
| 0 | 154 intr->dsr( intr->vector, 1, (CYG_ADDRWORD)intr->data ); |
| 155 } | |
| 156 | |
| 157 #endif | |
| 158 | |
| 159 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 160 | |
| 161 while( dsr_list != NULL ) | |
| 162 { | |
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163 Cyg_Interrupt* intr; |
| 0 | 164 cyg_uint32 old_intr; |
| 165 cyg_count32 count; | |
| 166 | |
| 167 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 168 | |
| 169 intr = dsr_list; | |
| 170 dsr_list = intr->next_dsr; | |
| 171 count = intr->dsr_count; | |
| 172 intr->dsr_count = 0; | |
| 173 | |
| 174 HAL_RESTORE_INTERRUPTS(old_intr); | |
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175 |
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176 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
| 0 | 177 |
| 178 intr->dsr( intr->vector, count, (CYG_ADDRWORD)intr->data ); | |
| 179 | |
| 180 } | |
| 181 | |
| 182 #endif | |
| 183 | |
| 184 }; | |
| 185 | |
| 2 | 186 externC void |
| 187 cyg_interrupt_call_pending_DSRs(void) | |
| 188 { | |
| 189 Cyg_Interrupt::call_pending_DSRs_inner(); | |
| 190 } | |
| 191 | |
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192 // |
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193 // Use HAL supported function to run through the DSRs, but executing using |
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194 // the separate interrupt stack if available. This function calls back |
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195 // into this module via 'cyg_interrupt_call_pending_DSRs' above, to keep |
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196 // the whole process as general as possible. |
| 2 | 197 |
| 198 void | |
| 199 Cyg_Interrupt::call_pending_DSRs(void) | |
| 200 { | |
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201 CYG_ASSERT( Cyg_Scheduler::get_sched_lock() == 1, |
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202 "DSRs being called with sched_lock not equal to 1"); |
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203 |
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204 HAL_INTERRUPT_STACK_CALL_PENDING_DSRS(); |
| 2 | 205 } |
| 206 | |
| 207 | |
| 0 | 208 // ------------------------------------------------------------------------- |
| 209 | |
| 2 | 210 void |
| 211 Cyg_Interrupt::post_dsr(void) | |
| 0 | 212 { |
| 213 // CYG_REPORT_FUNCTION(); | |
| 214 | |
| 215 CYG_INSTRUMENT_INTR(POST_DSR, vector, 0); | |
| 216 | |
| 217 cyg_uint32 old_intr; | |
| 218 | |
| 219 // We need to disable interrupts during this part to | |
| 220 // guard against nested interrupts. | |
| 221 | |
| 222 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 223 | |
| 224 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 225 | |
| 226 dsr_table[dsr_table_tail++] = this; | |
| 227 if( dsr_table_tail >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) | |
| 228 dsr_table_tail = 0; | |
| 229 | |
| 230 #endif | |
| 231 | |
| 232 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 233 | |
| 234 // Only add the interrupt to the dsr list if this is | |
| 235 // the first DSR call. | |
| 236 // At present DSRs are pushed onto the list and will be | |
| 237 // called in reverse order. We do not define the order | |
| 238 // in which DSRs are called, so this is acceptable. | |
| 239 | |
| 240 if( dsr_count++ == 0 ) | |
| 241 { | |
| 242 next_dsr = dsr_list; | |
| 243 dsr_list = this; | |
| 244 } | |
| 245 | |
| 246 #endif | |
| 247 | |
| 248 HAL_RESTORE_INTERRUPTS(old_intr); | |
| 249 }; | |
| 250 | |
| 251 // ------------------------------------------------------------------------- | |
| 2 | 252 // A C callable interface to Cyg_Interrupt::post_dsr() that can be used from |
| 253 // the HAL. | |
| 0 | 254 |
| 2 | 255 externC void |
| 256 cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj ) | |
| 257 { | |
| 258 Cyg_Interrupt* intr = (Cyg_Interrupt*) intr_obj; | |
| 259 intr->post_dsr (); | |
| 260 } | |
| 261 | |
| 262 // ------------------------------------------------------------------------- | |
| 263 | |
| 264 // FIXME: should have better name - Jifl | |
| 265 externC void | |
| 266 interrupt_end( | |
| 0 | 267 cyg_uint32 isr_ret, |
| 268 Cyg_Interrupt *intr, | |
| 269 HAL_SavedRegisters *regs | |
| 270 ) | |
| 271 { | |
| 272 // CYG_REPORT_FUNCTION(); | |
| 273 | |
| 2 | 274 // Sometimes we have a NULL intr object pointer. |
| 275 cyg_vector vector = (intr!=NULL)?intr->vector:0; | |
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276 |
| 2 | 277 CYG_INSTRUMENT_INTR(END, vector, isr_ret); |
| 278 | |
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279 CYG_UNUSED_PARAM( cyg_vector, vector ); // prevent compiler warning |
| 2 | 280 |
| 0 | 281 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
| 282 | |
| 283 // Only do this if we are in a non-chained configuration. | |
| 284 // If we are chained, then chain_isr below will do the DSR | |
| 285 // posting. | |
| 286 | |
| 2 | 287 if( isr_ret & Cyg_Interrupt::CALL_DSR && intr != NULL ) intr->post_dsr(); |
| 0 | 288 |
| 289 #endif | |
| 290 | |
| 291 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 292 | |
| 293 // If we have GDB support enabled, and there is the possibility | |
| 294 // that this thread will be context switched as a result of this | |
| 295 // interrupt, then save the pointer to the saved thread context in | |
| 296 // the thread object so that GDB can get a meaningful context to | |
| 297 // look at. | |
| 298 | |
| 299 Cyg_Scheduler::get_current_thread()->set_saved_context(regs); | |
| 300 | |
| 301 #endif | |
| 302 | |
| 303 // Now unlock the scheduler, which may also call DSRs | |
| 304 // and cause a thread switch to happen. | |
| 305 | |
| 306 Cyg_Scheduler::unlock(); | |
| 307 | |
| 308 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 309 | |
| 310 Cyg_Scheduler::get_current_thread()->set_saved_context(0); | |
| 311 | |
| 312 #endif | |
| 313 | |
| 2 | 314 CYG_INSTRUMENT_INTR(RESTORE, vector, 0); |
| 0 | 315 } |
| 316 | |
| 317 // ------------------------------------------------------------------------- | |
| 318 // Interrupt chaining statics. | |
| 319 | |
| 320 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 321 | |
| 2 | 322 Cyg_Interrupt *Cyg_Interrupt::chain_list[CYGNUM_HAL_ISR_COUNT]; |
| 0 | 323 |
| 324 #endif | |
| 325 | |
| 326 // ------------------------------------------------------------------------- | |
| 327 // Chaining ISR inserted in HAL vector | |
| 328 | |
| 329 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 330 | |
| 2 | 331 cyg_uint32 |
| 332 Cyg_Interrupt::chain_isr(cyg_vector vector, CYG_ADDRWORD data) | |
| 0 | 333 { |
| 334 Cyg_Interrupt *p = *(Cyg_Interrupt **)data; | |
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335 register cyg_uint32 isr_ret = 0; |
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336 register cyg_uint32 isr_chain_ret = 0; |
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337 |
| 0 | 338 CYG_INSTRUMENT_INTR(CHAIN_ISR, vector, 0); |
| 339 | |
| 340 while( p != NULL ) | |
| 341 { | |
| 342 if( p->vector == vector ) | |
| 343 { | |
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344 isr_ret = p->isr(vector, p->data); |
| 0 | 345 |
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346 isr_chain_ret |= isr_ret; |
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347 |
| 2 | 348 if( isr_ret & Cyg_Interrupt::CALL_DSR ) p->post_dsr(); |
| 0 | 349 |
| 2 | 350 if( isr_ret & Cyg_Interrupt::HANDLED ) break; |
| 0 | 351 } |
| 352 | |
| 353 p = p->next; | |
| 354 } | |
| 355 | |
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356 #ifdef HAL_DEFAULT_ISR |
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357 if( (isr_chain_ret & (Cyg_Interrupt::HANDLED|Cyg_Interrupt::CALL_DSR)) == 0 ) |
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358 { |
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359 // If we finished the loop for some reason other than that an |
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360 // ISR has handled the interrupt, call any default ISR to either |
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361 // report the spurious interrupt, or do some other HAL level processing |
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362 // such as GDB interrupt detection etc. |
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363 |
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364 HAL_DEFAULT_ISR( vector, 0 ); |
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365 } |
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366 #endif |
| 0 | 367 return 0; |
| 368 } | |
| 369 | |
| 370 #endif | |
| 371 | |
| 372 // ------------------------------------------------------------------------- | |
| 373 // Attach an ISR to an interrupt vector. | |
| 374 | |
| 2 | 375 void |
| 376 Cyg_Interrupt::attach(void) | |
| 0 | 377 { |
| 378 CYG_REPORT_FUNCTION(); | |
| 379 | |
| 2 | 380 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 381 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 382 |
| 383 CYG_INSTRUMENT_INTR(ATTACH, vector, 0); | |
| 384 | |
| 385 HAL_INTERRUPT_SET_LEVEL( vector, priority ); | |
| 386 | |
| 387 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 388 | |
| 389 CYG_ASSERT( next == NULL , "Cyg_Interrupt already on a list"); | |
| 390 | |
| 391 cyg_uint32 index; | |
| 392 | |
| 393 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 394 | |
| 395 if( chain_list[index] == NULL ) | |
| 396 { | |
| 2 | 397 int in_use; |
| 0 | 398 // First Interrupt on this chain, just assign it and register |
| 399 // the chain_isr with the HAL. | |
| 400 | |
| 401 chain_list[index] = this; | |
| 402 | |
| 2 | 403 HAL_INTERRUPT_IN_USE( vector, in_use ); |
| 404 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 0 | 405 HAL_INTERRUPT_ATTACH( vector, chain_isr, &chain_list[index], NULL ); |
| 406 } | |
| 407 else | |
| 408 { | |
| 409 // There are already interrupts chained, add this one into the | |
| 410 // chain in priority order. | |
| 411 | |
| 412 Cyg_Interrupt **p = &chain_list[index]; | |
| 413 | |
| 414 while( *p != NULL ) | |
| 415 { | |
| 416 Cyg_Interrupt *n = *p; | |
| 417 | |
| 418 if( n->priority < priority ) break; | |
| 419 | |
| 420 p = &n->next; | |
| 421 } | |
| 422 next = *p; | |
| 423 *p = this; | |
| 424 } | |
| 425 | |
| 426 #else | |
| 427 | |
| 2 | 428 { |
| 429 int in_use; | |
| 430 | |
| 431 | |
| 432 HAL_INTERRUPT_IN_USE( vector, in_use ); | |
| 433 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 434 | |
| 435 HAL_INTERRUPT_ATTACH( vector, isr, data, this ); | |
| 436 } | |
| 0 | 437 |
| 438 #endif | |
| 2 | 439 CYG_REPORT_RETURN(); |
| 0 | 440 } |
| 441 | |
| 442 // ------------------------------------------------------------------------- | |
| 443 // Detach the ISR from the vector | |
| 444 | |
| 2 | 445 void |
| 446 Cyg_Interrupt::detach(void) | |
| 0 | 447 { |
| 448 CYG_REPORT_FUNCTION(); | |
| 449 | |
| 2 | 450 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 451 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 452 |
| 453 CYG_INSTRUMENT_INTR(DETACH, vector, 0); | |
| 454 | |
| 455 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 456 | |
| 457 // Remove the interrupt object from the vector chain. | |
| 458 | |
| 2 | 459 cyg_uint32 index; |
| 460 | |
| 461 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 462 | |
| 463 Cyg_Interrupt **p = &chain_list[index]; | |
| 0 | 464 |
| 465 while( *p != NULL ) | |
| 466 { | |
| 467 Cyg_Interrupt *n = *p; | |
| 468 | |
| 469 if( n == this ) | |
| 470 { | |
| 471 *p = next; | |
| 472 break; | |
| 473 } | |
| 474 | |
| 475 p = &n->next; | |
| 476 } | |
| 477 | |
| 478 // If this was the last one, detach the vector. | |
| 479 | |
| 2 | 480 if( chain_list[index] == NULL ) |
| 0 | 481 HAL_INTERRUPT_DETACH( vector, chain_isr ); |
| 482 | |
| 483 #else | |
| 484 | |
| 485 HAL_INTERRUPT_DETACH( vector, isr ); | |
| 486 | |
| 487 #endif | |
| 2 | 488 |
| 489 CYG_REPORT_RETURN(); | |
| 0 | 490 |
| 491 } | |
| 492 | |
| 493 // ------------------------------------------------------------------------- | |
| 494 // Get the current service routine | |
| 495 | |
| 2 | 496 void |
| 497 Cyg_Interrupt::get_vsr(cyg_vector vector, cyg_VSR **vsr) | |
| 0 | 498 { |
| 499 CYG_REPORT_FUNCTION(); | |
| 2 | 500 CYG_REPORT_FUNCARG2("vector = %d, mem to put VSR in is at %08x", vector, |
| 501 vsr); | |
| 0 | 502 |
| 2 | 503 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 504 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 505 |
| 506 HAL_VSR_GET( vector, vsr ); | |
| 2 | 507 |
| 508 CYG_REPORT_RETURN(); | |
| 0 | 509 } |
| 510 | |
| 511 // ------------------------------------------------------------------------- | |
| 512 // Install a vector service routine | |
| 513 | |
| 2 | 514 void |
| 515 Cyg_Interrupt::set_vsr(cyg_vector vector, cyg_VSR *vsr, cyg_VSR **old) | |
| 0 | 516 { |
| 517 CYG_REPORT_FUNCTION(); | |
| 518 | |
| 2 | 519 CYG_REPORT_FUNCARG3( "vector = %d, new vsr is at %08x, mem to put " |
| 520 "old VSR in is at %08x", vector, vsr, old); | |
| 521 | |
| 0 | 522 CYG_INSTRUMENT_INTR(SET_VSR, vector, vsr); |
| 523 | |
| 2 | 524 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 525 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 526 |
| 527 CYG_INTERRUPT_STATE old_ints; | |
| 528 | |
| 529 HAL_DISABLE_INTERRUPTS(old_ints); | |
| 530 | |
| 531 HAL_VSR_SET( vector, vsr, old ); | |
| 532 | |
| 533 HAL_RESTORE_INTERRUPTS(old_ints); | |
| 2 | 534 |
| 535 CYG_REPORT_RETURN(); | |
| 0 | 536 } |
| 537 | |
| 538 // ------------------------------------------------------------------------- | |
| 539 // Disable interrupts at the CPU | |
| 540 | |
| 541 | |
| 2 | 542 void |
| 543 Cyg_Interrupt::disable_interrupts(void) | |
| 0 | 544 { |
| 545 CYG_REPORT_FUNCTION(); | |
| 546 | |
| 2 | 547 CYG_INSTRUMENT_INTR(DISABLE, disable_counter+1, 0); |
| 0 | 548 |
| 549 CYG_INTERRUPT_STATE dummy; | |
| 550 | |
| 551 HAL_DISABLE_INTERRUPTS(dummy); | |
| 552 | |
| 2 | 553 CYG_ASSERT( disable_counter >= 0 , "Disable counter negative"); |
| 554 | |
| 555 disable_counter++; | |
| 556 | |
| 557 CYG_REPORT_RETURN(); | |
| 0 | 558 } |
| 559 | |
| 560 | |
| 561 // ------------------------------------------------------------------------- | |
| 562 // Re-enable CPU interrupts | |
| 563 | |
| 2 | 564 void |
| 565 Cyg_Interrupt::enable_interrupts(void) | |
| 0 | 566 { |
| 567 CYG_REPORT_FUNCTION(); | |
| 568 | |
| 2 | 569 CYG_INSTRUMENT_INTR(ENABLE, disable_counter, 0); |
| 570 | |
| 571 CYG_ASSERT( disable_counter > 0 , "Disable counter not greater than zero"); | |
| 572 | |
| 573 disable_counter--; | |
| 0 | 574 |
| 2 | 575 if ( disable_counter == 0 ) |
| 576 { | |
| 577 HAL_ENABLE_INTERRUPTS(); | |
| 578 } | |
| 579 | |
| 580 CYG_REPORT_RETURN(); | |
| 0 | 581 } |
| 582 | |
| 583 // ------------------------------------------------------------------------- | |
| 584 // Mask a specific interrupt in a PIC | |
| 585 | |
| 2 | 586 void |
| 587 Cyg_Interrupt::mask_interrupt(cyg_vector vector) | |
| 0 | 588 { |
| 589 CYG_REPORT_FUNCTION(); | |
| 2 | 590 CYG_REPORT_FUNCARG1("vector=%d", vector); |
| 0 | 591 |
| 2 | 592 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 593 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 594 |
| 595 CYG_INSTRUMENT_INTR(MASK, vector, 0); | |
| 596 | |
| 2 | 597 HAL_INTERRUPT_MASK( vector ); |
| 598 | |
| 599 CYG_REPORT_RETURN(); | |
| 0 | 600 } |
| 601 | |
| 602 // ------------------------------------------------------------------------- | |
| 603 // Clear PIC mask | |
| 604 | |
| 2 | 605 void |
| 606 Cyg_Interrupt::unmask_interrupt(cyg_vector vector) | |
| 0 | 607 { |
| 608 CYG_REPORT_FUNCTION(); | |
| 609 | |
| 2 | 610 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 611 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 612 |
| 613 CYG_INSTRUMENT_INTR(UNMASK, vector, 0); | |
| 614 | |
| 615 HAL_INTERRUPT_UNMASK( vector ); | |
| 2 | 616 |
| 617 CYG_REPORT_RETURN(); | |
| 0 | 618 } |
| 619 | |
| 620 | |
| 621 // ------------------------------------------------------------------------- | |
| 622 // Acknowledge interrupt at PIC | |
| 623 | |
| 2 | 624 void |
| 625 Cyg_Interrupt::acknowledge_interrupt(cyg_vector vector) | |
| 0 | 626 { |
| 627 // CYG_REPORT_FUNCTION(); | |
| 628 | |
| 2 | 629 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 630 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 631 |
| 632 CYG_INSTRUMENT_INTR(ACK, vector, 0); | |
| 633 | |
| 634 HAL_INTERRUPT_ACKNOWLEDGE( vector ); | |
| 635 } | |
| 636 | |
| 637 // ------------------------------------------------------------------------- | |
| 638 // Change interrupt detection at PIC | |
| 639 | |
| 2 | 640 void |
| 641 Cyg_Interrupt::configure_interrupt( | |
| 0 | 642 cyg_vector vector, // vector to control |
| 643 cyg_bool level, // level or edge triggered | |
| 644 cyg_bool up // hi/lo level, rising/falling edge | |
| 645 ) | |
| 646 { | |
| 647 CYG_REPORT_FUNCTION(); | |
| 2 | 648 CYG_REPORT_FUNCARG3("vector = %d, level = %d, up = %d", vector, level, |
| 649 up); | |
| 0 | 650 |
| 2 | 651 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 652 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 653 |
| 654 CYG_INSTRUMENT_INTR(CONFIGURE, vector, (level<<1)|up); | |
| 655 | |
| 656 HAL_INTERRUPT_CONFIGURE( vector, level, up ); | |
| 2 | 657 |
| 658 CYG_REPORT_RETURN(); | |
| 0 | 659 } |
| 660 | |
| 661 // ------------------------------------------------------------------------- | |
| 662 // EOF intr/intr.cxx |