nand-ecoscentric: packages/hal/mips/arch/current/include/hal

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 76:435cced73e2f ecos-v1_3_1-release

eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST

author	jlarmour
date	Tue, 28 Mar 2000 14:10:45 +0000
parents	bf00f99aec69
children	08ffab08d2ee

rev	line source
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	1 #ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 #define CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	6 // hal_cache.h
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	7 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	8 // HAL cache control API
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	11 //####COPYRIGHTBEGIN####
64 c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	12 //
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	13 // -------------------------------------------
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	14 // The contents of this file are subject to the Red Hat eCos Public License
66 bf00f99aec69 Merge from eCos master repository on 2000-02-02-19:16:44-GMT jlarmour parents: 64 diff changeset	15 // Version 1.1 (the "License"); you may not use this file except in
64 c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	16 // compliance with the License. You may obtain a copy of the License at
66 bf00f99aec69 Merge from eCos master repository on 2000-02-02-19:16:44-GMT jlarmour parents: 64 diff changeset	17 // http://www.redhat.com/
64 c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	18 //
66 bf00f99aec69 Merge from eCos master repository on 2000-02-02-19:16:44-GMT jlarmour parents: 64 diff changeset	19 // Software distributed under the License is distributed on an "AS IS"
64 c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	21 // License for the specific language governing rights and limitations under
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	22 // the License.
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	23 //
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	24 // The Original Code is eCos - Embedded Configurable Operating System,
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	25 // released September 30, 1998.
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	26 //
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	27 // The Initial Developer of the Original Code is Red Hat.
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	28 // Portions created by Red Hat are
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	29 // Copyright (C) 1998, 1999, 2000 Red Hat, Inc.
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	30 // All Rights Reserved.
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	31 // -------------------------------------------
c38311975d4f Merge from eCos master repository on 2000-01-28-04:28:11-GMT jlarmour parents: 24 diff changeset	32 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	33 //####COPYRIGHTEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	34 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	35 //#####DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	36 //
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	37 // Author(s): nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	38 // Contributors: nickg
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	39 // Date: 1998-02-17
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	40 // Purpose: Cache control API
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	41 // Description: The macros defined here provide the HAL APIs for handling
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	42 // cache control operations.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	43 // Usage:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	44 // #include <cyg/hal/hal_cache.h>
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	45 // ...
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	46 //
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	47 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	48 //####DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	49 //
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	50 //=============================================================================
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	51
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	52 #include <pkgconf/hal.h>
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	53 #include <cyg/infra/cyg_type.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	54
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	55 #include <cyg/hal/var_cache.h>
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	56
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	57 // Use this macro to allow the assembler to accept "cache" instructions,
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	58 // which are MIPS ISA 3. This is useful if someone is compiling
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	59 // with -mips2, but the architecture is really MIPS ISA 3.
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	60
76 435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	61 #define _hal_asm_mips_cpp_stringize( _x_ ) #_x_
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	62 #define _HAL_ASM_SET_MIPS_ISA( _isal_ ) asm volatile ( \
435cced73e2f eCos v1.3.1 merged from eCos master repository on 2000-03-27-23:22:51-BST jlarmour parents: 66 diff changeset	63 ".set mips" ## _hal_asm_mips_cpp_stringize(_isal_) )
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	64
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	65
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	66 //=============================================================================
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	67 // Default Implementation. This uses the standard MIPS CP0 registers and
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	68 // cache instructions. Note that not all variants will have all of the
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	69 // functionality defined here.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	70
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	71 //-----------------------------------------------------------------------------
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	72 // Cache dimensions.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	73 // These really should be defined in var_cache.h. If they are not, then provide
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	74 // a set of numbers that are typical of many variants.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	75
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	76 #ifndef HAL_DCACHE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	77
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	78 // Data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	79 #define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	80 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	81 #define HAL_DCACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	82
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	83 // Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	84 #define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	85 #define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	86 #define HAL_ICACHE_WAYS 2 // Associativity of the cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	87
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	88 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	89 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	90
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	91 #endif
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	92
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	93 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	94 // Global control of data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	95
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	96 // Enable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	97 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	98 #ifndef HAL_DCACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	99 #define HAL_DCACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	100 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	101
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	102 // Disable the data cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	103 #ifndef HAL_DCACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	104 #define HAL_DCACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	105 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	106
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	107 #ifndef HAL_DCACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	108 #define HAL_DCACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	109 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	110
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	111 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	112 // We simply use HAL_DCACHE_SYNC() to do this. For writeback caches this
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	113 // is not quite what we want, but there is no index-invalidate operation
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	114 // available.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	115 #ifndef HAL_DCACHE_INVALIDATE_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	116 #define HAL_DCACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	117 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	118
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	119 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	120 // This uses the index-writeback-invalidate operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	121 #ifndef HAL_DCACHE_SYNC_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	122 #define HAL_DCACHE_SYNC() \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	123 { \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	124 register CYG_ADDRESS _baddr_ = 0x80000000; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	125 register CYG_ADDRESS _addr_ = 0x80000000; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	126 register CYG_WORD _size_ = HAL_DCACHE_SIZE; \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	127 _HAL_ASM_SET_MIPS_ISA(3); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	128 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	129 { asm volatile ("cache 0x01,0(%0)" : : "r"(_addr_) ); } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	130 _HAL_ASM_SET_MIPS_ISA(0); \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	131 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	132 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	133
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	134 // Set the data cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	135 //#define HAL_DCACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	136
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	137 // Set the data cache write mode
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	138 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	139
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	140 //#define HAL_DCACHE_WRITETHRU_MODE 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	141 //#define HAL_DCACHE_WRITEBACK_MODE 1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	142
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	143 // Load the contents of the given address range into the data cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	144 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	145 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	146 #ifndef HAL_DCACHE_LOCK_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	147 #define HAL_DCACHE_LOCK(_base_, _asize_) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	148 CYG_MACRO_START \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	149 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	150 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	151 register CYG_WORD _size_ = (_asize_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	152 register CYG_WORD _state_; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	153 HAL_DCACHE_IS_ENABLED( _state_ ); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	154 if( _state_ ) { \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	155 _HAL_ASM_SET_MIPS_ISA(3); \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	156 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	157 { asm volatile ("cache 0x1d,0(%0)" : : "r"(_addr_) ); } \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	158 _HAL_ASM_SET_MIPS_ISA(0); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	159 } \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	160 CYG_MACRO_END
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	161 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	162
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	163 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	164 // Do this by flushing the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	165 #ifndef HAL_DCACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	166 #define HAL_DCACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	167 HAL_DCACHE_FLUSH( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	168 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	169
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	170 // Unlock entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	171 #ifndef HAL_DCACHE_UNLOCK_ALL_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	172 #define HAL_DCACHE_UNLOCK_ALL() \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	173 HAL_DCACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	174 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	175
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	176 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	177 // Data cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	178
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	179 // Allocate cache lines for the given address range without reading its
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	180 // contents from memory.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	181 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	182
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	183 // Write dirty cache lines to memory and invalidate the cache entries
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	184 // for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	185 // This uses the hit-writeback-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	186 #ifndef HAL_DCACHE_FLUSH_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	187 #define HAL_DCACHE_FLUSH( _base_ , _asize_ ) \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	188 CYG_MACRO_START \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	189 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	190 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	191 register CYG_WORD _size_ = (_asize_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	192 register CYG_WORD _state_; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	193 HAL_DCACHE_IS_ENABLED( _state_ ); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	194 if( _state_ ) { \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	195 _HAL_ASM_SET_MIPS_ISA(3); \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	196 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	197 { asm volatile ("cache 0x15,0(%0)" : : "r"(_addr_) ); } \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	198 _HAL_ASM_SET_MIPS_ISA(0); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	199 } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	200 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	201 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	202
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	203 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	204 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	205 #ifndef HAL_DCACHE_INVALIDATE_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	206 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	207 { \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	208 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	209 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	210 register CYG_WORD _size_ = (_asize_); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	211 _HAL_ASM_SET_MIPS_ISA(3); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	212 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	213 { asm volatile ("cache 0x11,0(%0)" : : "r"(_addr_) ); } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	214 _HAL_ASM_SET_MIPS_ISA(0); \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	215 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	216 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	217
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	218 // Write dirty cache lines to memory for the given address range.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	219 // This uses the hit-writeback cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	220 #ifndef HAL_DCACHE_STORE_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	221 #define HAL_DCACHE_STORE( _base_ , _asize_ ) \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	222 CYG_MACRO_START \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	223 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	224 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	225 register CYG_WORD _size_ = (_asize_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	226 register CYG_WORD _state_; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	227 HAL_DCACHE_IS_ENABLED( _state_ ); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	228 if( _state_ ) { \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	229 _HAL_ASM_SET_MIPS_ISA(3); \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	230 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	231 { asm volatile ("cache 0x19,0(%0)" : : "r"(_addr_) ); } \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	232 _HAL_ASM_SET_MIPS_ISA(0); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	233 } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	234 CYG_MACRO_END
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	235 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	236
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	237 // Preread the given range into the cache with the intention of reading
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	238 // from it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	239 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	240
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	241 // Preread the given range into the cache with the intention of writing
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	242 // to it later.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	243 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	244
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	245 // Allocate and zero the cache lines associated with the given range.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	246 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	247
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	248 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	249 // Global control of Instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	250
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	251 // Enable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	252 // There is no default mechanism for enabling or disabling the caches.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	253 #ifndef HAL_ICACHE_ENABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	254 #define HAL_ICACHE_ENABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	255 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	256
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	257 // Disable the instruction cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	258 #ifndef HAL_ICACHE_DISABLE_DEFINED
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	259 #define HAL_ICACHE_DISABLE()
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	260 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	261
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	262 #ifndef HAL_ICACHE_IS_ENABLED_DEFINED
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	263 #define HAL_ICACHE_IS_ENABLED(_state_) (_state_) = 1;
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	264 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 6 diff changeset	265
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	266 // Invalidate the entire cache
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	267 // This uses the index-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	268 #ifndef HAL_ICACHE_INVALIDATE_ALL_DEFINED
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	269 #define HAL_ICACHE_INVALIDATE_ALL() \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	270 { \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	271 register CYG_ADDRESS _baddr_ = 0x80000000; \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	272 register CYG_ADDRESS _addr_ = 0x80000000; \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	273 _HAL_ASM_SET_MIPS_ISA(3); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	274 for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	275 { asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	276 _HAL_ASM_SET_MIPS_ISA(0); \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	277 }
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	278 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	279
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	280 // Synchronize the contents of the cache with memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	281 // Simply force the cache to reload.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	282 #ifndef HAL_ICACHE_SYNC_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	283 #define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	284 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	285
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	286 // Set the instruction cache refill burst size
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	287 //#define HAL_ICACHE_BURST_SIZE(_size_)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	288
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	289 // Load the contents of the given address range into the instruction cache
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	290 // and then lock the cache so that it stays there.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	291 // This uses the fetch-and-lock cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	292 #ifndef HAL_ICACHE_LOCK_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	293 #define HAL_ICACHE_LOCK(_base_, _asize_) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	294 CYG_MACRO_START \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	295 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	296 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	297 register CYG_WORD _size_ = (_asize_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	298 register CYG_WORD _state_; \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	299 HAL_ICACHE_IS_ENABLED( _state_ ); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	300 if( _state_ ) { \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	301 _HAL_ASM_SET_MIPS_ISA(3); \
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	302 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	303 { asm volatile ("cache 0x1c,0(%0)" : : "r"(_addr_) ); } \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	304 _HAL_ASM_SET_MIPS_ISA(0); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	305 } \
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	306 CYG_MACRO_END
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	307 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	308
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	309 // Undo a previous lock operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	310 // Do this by invalidating the cache, which is defined to clear the lock bit.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	311 #ifndef HAL_ICACHE_UNLOCK_DEFINED
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	312 #define HAL_ICACHE_UNLOCK(_base_, _size_) \
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	313 HAL_ICACHE_INVALIDATE( _base_, _size_ )
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	314 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	315
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	316 // Unlock entire cache
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	317 //#define HAL_ICACHE_UNLOCK_ALL()
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	318
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	319 //-----------------------------------------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	320 // Instruction cache line control
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	321
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	322 // Invalidate cache lines in the given range without writing to memory.
6 d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	323 // This uses the hit-invalidate cache operation.
d376b777e2ce Merge from eCos master repository on 1999-05-14-19:27:43-BST jlarmour parents: 2 diff changeset	324 #ifndef HAL_ICACHE_INVALIDATE_DEFINED
18 7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	325 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	326 { \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	327 register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	328 register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
7253dcc42a09 Merge from eCos master repository on 1999-06-25-15:31:50-BST jlarmour parents: 10 diff changeset	329 register CYG_WORD _size_ = (_asize_); \
24 306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	330 _HAL_ASM_SET_MIPS_ISA(3); \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	331 for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	332 { asm volatile ("cache 0x10,0(%0)" : : "r"(_addr_) ); } \
306eee292492 Merge from eCos master repository on 1999-07-16-05:47:06-BST jlarmour parents: 18 diff changeset	333 _HAL_ASM_SET_MIPS_ISA(0); \
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	334 }
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	335 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	336
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	337 //-----------------------------------------------------------------------------
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	338 // Check that a supported configuration has actually defined some macros.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	339
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	340 #ifndef HAL_DCACHE_ENABLE
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	341
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	342 #error Unsupported MIPS configuration
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	343
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	344 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	345
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	346 //-----------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	347 #endif // ifndef CYGONCE_HAL_CACHE_H
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	348 // End of hal_cache.h

Mercurial > nand-ecoscentric

annotate packages/hal/mips/arch/current/include/hal_cache.h @ 76:435cced73e2f ecos-v1_3_1-release