Mercurial > ecos
annotate packages/hal/mips/arch/current/include/hal_arch.h @ 18:7253dcc42a09 ecos-sw-1999-06-25
Merge from eCos master repository on 1999-06-25-15:31:50-BST
| author | jlarmour |
|---|---|
| date | Fri, 25 Jun 1999 08:28:05 +0000 |
| parents | 01ce82f3e11a |
| children | 7a6ac9edc838 |
| rev | line source |
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| 0 | 1 #ifndef CYGONCE_HAL_HAL_ARCH_H |
| 2 #define CYGONCE_HAL_HAL_ARCH_H | |
| 3 | |
| 2 | 4 //========================================================================== |
| 0 | 5 // |
| 2 | 6 // hal_arch.h |
| 0 | 7 // |
| 2 | 8 // Architecture specific abstractions |
| 0 | 9 // |
| 2 | 10 //========================================================================== |
| 0 | 11 //####COPYRIGHTBEGIN#### |
| 12 // | |
| 13 // ------------------------------------------- | |
| 14 // The contents of this file are subject to the Cygnus eCos Public License | |
| 15 // Version 1.0 (the "License"); you may not use this file except in | |
| 16 // compliance with the License. You may obtain a copy of the License at | |
| 17 // http://sourceware.cygnus.com/ecos | |
| 18 // | |
| 19 // Software distributed under the License is distributed on an "AS IS" | |
| 20 // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the | |
| 21 // License for the specific language governing rights and limitations under | |
| 22 // the License. | |
| 23 // | |
| 24 // The Original Code is eCos - Embedded Cygnus Operating System, released | |
| 25 // September 30, 1998. | |
| 26 // | |
| 27 // The Initial Developer of the Original Code is Cygnus. Portions created | |
| 2 | 28 // by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved. |
| 0 | 29 // ------------------------------------------- |
| 30 // | |
| 31 //####COPYRIGHTEND#### | |
| 2 | 32 //========================================================================== |
| 0 | 33 //#####DESCRIPTIONBEGIN#### |
| 34 // | |
| 2 | 35 // Author(s): nickg |
| 36 // Contributors: nickg | |
| 37 // Date: 1999-02-17 | |
| 38 // Purpose: Define architecture abstractions | |
| 39 // Usage: #include <cyg/hal/hal_arch.h> | |
| 40 // | |
| 0 | 41 //####DESCRIPTIONEND#### |
| 42 // | |
| 2 | 43 //========================================================================== |
| 0 | 44 |
| 2 | 45 #include <pkgconf/hal.h> |
| 0 | 46 #include <cyg/infra/cyg_type.h> |
| 47 | |
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48 #include <cyg/hal/var_arch.h> |
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49 |
| 2 | 50 //-------------------------------------------------------------------------- |
| 0 | 51 // Processor saved states: |
| 52 // The layout of this structure is also defined in "mips.inc", for assembly | |
| 53 // code. Do not change this without changing that (or vice versa). | |
| 54 | |
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55 #if defined(CYGHWR_HAL_MIPS_FPU) |
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56 # if defined(CYGHWR_HAL_MIPS_FPU_64BIT) |
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57 # define CYG_HAL_FPU_REG CYG_WORD64 |
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58 # elif defined(CYGHWR_HAL_MIPS_FPU_32BIT) |
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59 # define CYG_HAL_FPU_REG CYG_WORD32 |
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60 # else |
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61 # error MIPS FPU register size not defined |
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62 # endif |
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63 #endif |
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64 |
| 0 | 65 typedef struct |
| 66 { | |
| 67 // These are common to all saved states | |
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68 CYG_ADDRWORD d[32]; /* Data regs */ |
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69 CYG_ADDRWORD hi; /* hi word of mpy/div reg */ |
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70 CYG_ADDRWORD lo; /* lo word of mpy/div reg */ |
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71 #ifdef CYGHWR_HAL_MIPS_FPU |
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72 CYG_HAL_FPU_REG f[32]; /* FPU registers */ |
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73 CYG_ADDRWORD fcr31; /* FPU control/status register */ |
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74 CYG_ADDRWORD fppad; /* Dummy location to make this */ |
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75 /* structure a multiple of 8 */ |
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76 /* bytes long. */ |
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77 #endif |
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78 |
| 0 | 79 // These are only saved for exceptions and interrupts |
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80 CYG_ADDRWORD vector; /* Vector number */ |
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81 CYG_ADDRWORD pc; /* Program Counter */ |
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82 CYG_ADDRWORD sr; /* Status Reg */ |
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83 CYG_ADDRWORD cache; /* Cache control register */ |
| 0 | 84 |
| 85 | |
| 86 // These are only saved for exceptions, and are not restored | |
| 87 // when continued. | |
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88 CYG_ADDRWORD cause; /* Exception cause register */ |
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89 CYG_ADDRWORD badvr; /* Bad virtual address reg */ |
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90 CYG_ADDRWORD prid; /* Processor Version */ |
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91 CYG_ADDRWORD config; /* Config register */ |
| 0 | 92 } HAL_SavedRegisters; |
| 93 | |
| 2 | 94 //-------------------------------------------------------------------------- |
| 0 | 95 // Exception handling function. |
| 96 // This function is defined by the kernel according to this prototype. It is | |
| 97 // invoked from the HAL to deal with any CPU exceptions that the HAL does | |
| 98 // not want to deal with itself. It usually invokes the kernel's exception | |
| 99 // delivery mechanism. | |
| 100 | |
| 2 | 101 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); |
| 0 | 102 |
| 2 | 103 //-------------------------------------------------------------------------- |
| 0 | 104 // Bit manipulation macros |
| 105 | |
| 106 externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask); | |
| 107 externC cyg_uint32 hal_msbit_index(cyg_uint32 mask); | |
| 108 | |
| 109 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask); | |
| 110 | |
| 111 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask); | |
| 112 | |
| 2 | 113 //-------------------------------------------------------------------------- |
| 0 | 114 // Context Initialization |
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115 |
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116 |
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117 // Optional FPU context initialization |
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118 #ifdef CYGHWR_HAL_MIPS_FPU |
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119 #define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ) \ |
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120 { \ |
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121 for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->f[_i_] = (_id_)|0xFF00|_i_; \ |
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122 (_regs_)->fcr31 = 0x01000000; \ |
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123 } |
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124 #else |
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125 #define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ) |
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126 #endif |
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127 |
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128 |
| 0 | 129 // Initialize the context of a thread. |
| 130 // Arguments: | |
| 131 // _sparg_ name of variable containing current sp, will be written with new sp | |
| 132 // _thread_ thread object address, passed as argument to entry point | |
| 133 // _entry_ entry point address. | |
| 134 // _id_ bit pattern used in initializing registers, for debugging. | |
| 2 | 135 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \ |
| 136 { \ | |
| 137 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-56; \ | |
| 138 register HAL_SavedRegisters *_regs_; \ | |
| 139 int _i_; \ | |
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140 _sp_ = _sp_ & 0xFFFFFFF0; \ |
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141 _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters))&0xFFFFFFF0); \ |
| 2 | 142 for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_; \ |
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143 HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ); \ |
| 2 | 144 (_regs_)->d[29] = (CYG_WORD)(_sp_); /* SP = top of stack */ \ |
| 145 (_regs_)->d[04] = (CYG_WORD)(_thread_); /* R4 = arg1 = thread ptr */ \ | |
| 146 (_regs_)->lo = 0; /* LO = 0 */ \ | |
| 147 (_regs_)->hi = 0; /* HI = 0 */ \ | |
| 148 (_regs_)->d[30] = (CYG_WORD)(_sp_); /* FP = top of stack */ \ | |
| 149 (_regs_)->d[31] = (CYG_WORD)(_entry_); /* LR(d[31]) = entry point*/ \ | |
| 150 (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = entry point */ \ | |
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151 (_regs_)->sr = 0x00000001; /* SR = ls 3 bits only */ \ |
| 2 | 152 _sparg_ = (CYG_ADDRESS)_regs_; \ |
| 0 | 153 } |
| 154 | |
| 2 | 155 //-------------------------------------------------------------------------- |
| 0 | 156 // Context switch macros. |
| 157 // The arguments are pointers to locations where the stack pointer | |
| 158 // of the current thread is to be stored, and from where the sp of the | |
| 159 // next thread is to be fetched. | |
| 160 | |
| 161 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); | |
| 162 externC void hal_thread_load_context( CYG_ADDRESS to ) | |
| 163 __attribute__ ((noreturn)); | |
| 164 | |
| 165 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ | |
| 2 | 166 hal_thread_switch_context( (CYG_ADDRESS)_tspptr_, \ |
| 167 (CYG_ADDRESS)_fspptr_); | |
| 0 | 168 |
| 169 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ | |
| 170 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); | |
| 171 | |
| 2 | 172 //-------------------------------------------------------------------------- |
| 0 | 173 // Execution reorder barrier. |
| 174 // When optimizing the compiler can reorder code. In multithreaded systems | |
| 175 // where the order of actions is vital, this can sometimes cause problems. | |
| 176 // This macro may be inserted into places where reordering should not happen. | |
| 177 // The "memory" keyword is potentially unnecessary, but it is harmless to | |
| 178 // keep it. | |
| 179 | |
| 180 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) | |
| 181 | |
| 2 | 182 //-------------------------------------------------------------------------- |
| 0 | 183 // Breakpoint support |
| 2 | 184 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to |
| 185 // happen if executed. | |
| 186 // HAL_BREAKINST is the value of the breakpoint instruction and | |
| 187 // HAL_BREAKINST_SIZE is its size in bytes. | |
| 0 | 188 |
| 189 #define HAL_BREAKPOINT(_label_) \ | |
| 2 | 190 asm volatile (" .globl " #_label_ ";" \ |
| 0 | 191 #_label_":" \ |
| 2 | 192 " break 5" \ |
| 0 | 193 ); |
| 194 | |
| 195 #define HAL_BREAKINST 0x0005000d | |
| 196 | |
| 197 #define HAL_BREAKINST_SIZE 4 | |
| 198 | |
| 2 | 199 //-------------------------------------------------------------------------- |
| 0 | 200 // Thread register state manipulation for GDB support. |
| 201 | |
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202 // Default to a 32 bit register size for GDB register dumps. |
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203 #ifndef CYG_HAL_GDB_REG |
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204 #define CYG_HAL_GDB_REG CYG_WORD32 |
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205 #endif |
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206 |
| 0 | 207 // Translate a stack pointer as saved by the thread context macros above into |
| 208 // a pointer to a HAL_SavedRegisters structure. | |
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209 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ |
| 0 | 210 (_regs_) = (HAL_SavedRegisters *)(_sp_) |
| 211 | |
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212 // If the CPU has an FPU, we also need to move the FPU registers. |
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213 #ifdef CYGHWR_HAL_MIPS_FPU |
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214 #define HAL_GET_GDB_FPU_REGISTERS( _regval_ , _regs_ ) \ |
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215 CYG_MACRO_START \ |
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216 int _i_; \ |
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217 for( _i_ = 0; _i_ < 32; _i_++ ) \ |
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218 _regval_[38+_i_] = (_regs_)->f[_i_]; \ |
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219 _regval_[70] = (_regs_)->fcr31; \ |
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220 CYG_MACRO_END |
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221 #define HAL_SET_GDB_FPU_REGISTERS( _regs_ , _regval_ ) \ |
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222 CYG_MACRO_START \ |
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223 int _i_; \ |
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224 for( _i_ = 0; _i_ < 32; _i_++ ) \ |
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225 (_regs_)->f[_i_] = _regval_[38+_i_]; \ |
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226 (_regs_)->fcr31 = _regval_[70]; \ |
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227 CYG_MACRO_END |
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228 #else |
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229 #define HAL_GET_GDB_FPU_REGISTERS( _regval_ , _regs_ ) |
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230 #define HAL_SET_GDB_FPU_REGISTERS( _regs_ , _regval_ ) |
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231 #endif |
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232 |
| 0 | 233 // Copy a set of registers from a HAL_SavedRegisters structure into a |
| 234 // GDB ordered array. | |
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235 #define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \ |
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236 { \ |
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237 CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \ |
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238 int _i_; \ |
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239 \ |
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240 for( _i_ = 0; _i_ < 32; _i_++ ) \ |
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241 _regval_[_i_] = (_regs_)->d[_i_]; \ |
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242 \ |
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243 HAL_GET_GDB_FPU_REGISTERS( _regval_, _regs_ ); \ |
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244 \ |
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245 _regval_[32] = (_regs_)->sr; \ |
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246 _regval_[33] = (_regs_)->lo; \ |
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247 _regval_[34] = (_regs_)->hi; \ |
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248 _regval_[35] = (_regs_)->badvr; \ |
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249 _regval_[36] = (_regs_)->cause; \ |
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250 _regval_[37] = (_regs_)->pc; \ |
| 0 | 251 } |
| 252 | |
| 253 // Copy a GDB ordered array into a HAL_SavedRegisters structure. | |
| 254 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ | |
| 255 { \ | |
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256 CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \ |
| 0 | 257 int _i_; \ |
| 258 \ | |
| 259 for( _i_ = 0; _i_ < 32; _i_++ ) \ | |
| 260 (_regs_)->d[_i_] = _regval_[_i_]; \ | |
| 261 \ | |
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262 HAL_SET_GDB_FPU_REGISTERS( _regs_, _regval_ ); \ |
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263 \ |
| 0 | 264 (_regs_)->sr = _regval_[32]; \ |
| 265 (_regs_)->lo = _regval_[33]; \ | |
| 266 (_regs_)->hi = _regval_[34]; \ | |
| 267 (_regs_)->badvr = _regval_[35]; \ | |
| 268 (_regs_)->cause = _regval_[36]; \ | |
| 269 (_regs_)->pc = _regval_[37]; \ | |
| 270 } | |
| 271 | |
| 2 | 272 //-------------------------------------------------------------------------- |
| 0 | 273 // HAL setjmp |
| 2 | 274 // Note: These definitions are repeated in hal_arch.h. If changes are |
| 275 // required remember to update both sets. | |
| 0 | 276 |
| 2 | 277 #define CYGARC_JMP_BUF_SP 0 |
| 278 #define CYGARC_JMP_BUF_R16 1 | |
| 279 #define CYGARC_JMP_BUF_R17 2 | |
| 280 #define CYGARC_JMP_BUF_R18 3 | |
| 281 #define CYGARC_JMP_BUF_R19 4 | |
| 282 #define CYGARC_JMP_BUF_R20 5 | |
| 283 #define CYGARC_JMP_BUF_R21 6 | |
| 284 #define CYGARC_JMP_BUF_R22 7 | |
| 285 #define CYGARC_JMP_BUF_R23 8 | |
| 286 #define CYGARC_JMP_BUF_R28 9 | |
| 287 #define CYGARC_JMP_BUF_R30 10 | |
| 288 #define CYGARC_JMP_BUF_R31 11 | |
| 0 | 289 |
| 2 | 290 #define CYGARC_JMP_BUF_SIZE 12 |
| 291 | |
| 292 typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE]; | |
| 0 | 293 |
| 294 externC int hal_setjmp(hal_jmp_buf env); | |
| 295 externC void hal_longjmp(hal_jmp_buf env, int val); | |
| 296 | |
| 2 | 297 //------------------------------------------------------------------------- |
| 0 | 298 // Idle thread code. |
| 299 // This macro is called in the idle thread loop, and gives the HAL the | |
| 300 // chance to insert code. Typical idle thread behaviour might be to halt the | |
| 301 // processor. | |
| 302 | |
| 303 externC void hal_idle_thread_action(cyg_uint32 loop_count); | |
| 304 | |
| 305 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) | |
| 306 | |
| 2 | 307 //-------------------------------------------------------------------------- |
| 308 // Minimal and sensible stack sizes: the intention is that applications | |
| 309 // will use these to provide a stack size in the first instance prior to | |
| 310 // proper analysis. Idle thread stack should be this big. | |
| 311 | |
| 312 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. | |
| 313 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. | |
| 314 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! | |
| 315 | |
| 316 // We define quite large stack needs for SPARClite, for it requires 576 | |
| 317 // bytes (144 words) to process an interrupt and thread-switch, and | |
| 318 // momentarily, but needed in case of recursive interrupts, it needs 208 | |
| 319 // words - if a sequence of saves to push out other regsets is interrupted. | |
| 320 | |
| 321 // This is not a config option because it should not be adjusted except | |
| 322 // under "enough rope" sort of disclaimers. | |
| 323 | |
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324 // Typical case stack frame size: return link + 4 pushed registers + some locals. |
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325 #define CYGNUM_HAL_STACK_FRAME_SIZE (48) |
| 2 | 326 |
| 327 // Stack needed for a context switch: | |
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328 #if defined(CYGHWR_HAL_MIPS_FPU) |
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329 # if defined(CYGHWR_HAL_MIPS_FPU_64BIT) |
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330 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*4)+(32*8)) |
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331 # elif defined(CYGHWR_HAL_MIPS_FPU_32BIT) |
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332 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*4)+(32*4)) |
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333 # else |
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334 # error MIPS FPU register size not defined |
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335 # endif |
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336 #else |
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337 #define CYGNUM_HAL_STACK_CONTEXT_SIZE ((32+10)*4) |
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338 #endif |
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339 |
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340 |
| 2 | 341 |
| 342 // Interrupt + call to ISR, interrupt_end() and the DSR | |
| 343 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE) | |
| 344 | |
| 345 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 346 | |
| 347 // An interrupt stack which is large enough for all possible interrupt | |
| 348 // conditions (and only used for that purpose) exists. "User" stacks | |
| 349 // can be much smaller | |
| 350 | |
| 351 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \ | |
| 352 CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \ | |
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353 CYGNUM_HAL_STACK_FRAME_SIZE*8) |
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354 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (CYGNUM_HAL_STACK_SIZE_MINIMUM+1024) |
| 2 | 355 |
| 356 #else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 357 | |
| 358 // No separate interrupt stack exists. Make sure all threads contain | |
| 359 // a stack sufficiently large. | |
| 360 | |
| 361 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096) | |
| 362 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096) | |
| 363 | |
| 364 #endif | |
| 365 | |
| 366 //-------------------------------------------------------------------------- | |
| 0 | 367 #endif // CYGONCE_HAL_HAL_ARCH_H |
| 368 // End of hal_arch.h |
