Mercurial > ecos
annotate packages/kernel/current/src/intr/intr.cxx @ 3101:e8b153151417
Fix compiler warnings about unused variables. [ Bugzilla 1001505 ]
| author | grante |
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| date | Tue, 06 Mar 2012 18:56:34 +0000 |
| parents | 74dbf4c3f2e1 |
| children |
| rev | line source |
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| 0 | 1 //========================================================================== |
| 2 // | |
| 2 | 3 // intr/intr.cxx |
| 0 | 4 // |
| 2 | 5 // Interrupt class implementations |
| 0 | 6 // |
| 7 //========================================================================== | |
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8 // ####ECOSGPLCOPYRIGHTBEGIN#### |
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9 // ------------------------------------------- |
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10 // This file is part of eCos, the Embedded Configurable Operating System. |
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11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
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12 // |
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13 // eCos is free software; you can redistribute it and/or modify it under |
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14 // the terms of the GNU General Public License as published by the Free |
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15 // Software Foundation; either version 2 or (at your option) any later |
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16 // version. |
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17 // |
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18 // eCos is distributed in the hope that it will be useful, but WITHOUT |
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19 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 // for more details. |
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22 // |
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23 // You should have received a copy of the GNU General Public License |
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24 // along with eCos; if not, write to the Free Software Foundation, Inc., |
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25 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. |
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26 // |
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27 // As a special exception, if other files instantiate templates or use |
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28 // macros or inline functions from this file, or you compile this file |
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29 // and link it with other works to produce a work based on this file, |
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30 // this file does not by itself cause the resulting work to be covered by |
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31 // the GNU General Public License. However the source code for this file |
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32 // must still be made available in accordance with section (3) of the GNU |
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33 // General Public License v2. |
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34 // |
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35 // This exception does not invalidate any other reasons why a work based |
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36 // on this file might be covered by the GNU General Public License. |
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37 // ------------------------------------------- |
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38 // ####ECOSGPLCOPYRIGHTEND#### |
| 0 | 39 //========================================================================== |
| 40 //#####DESCRIPTIONBEGIN#### | |
| 41 // | |
| 2 | 42 // Author(s): nickg |
| 43 // Contributors: nickg | |
| 44 // Date: 1999-02-17 | |
| 45 // Purpose: Interrupt class implementation | |
| 46 // Description: This file contains the definitions of the interrupt | |
| 47 // class. | |
| 0 | 48 // |
| 49 //####DESCRIPTIONEND#### | |
| 50 // | |
| 51 //========================================================================== | |
| 52 | |
| 53 #include <pkgconf/kernel.h> | |
| 54 | |
| 55 #include <cyg/kernel/ktypes.h> // base kernel types | |
| 56 #include <cyg/infra/cyg_trac.h> // tracing macros | |
| 57 #include <cyg/infra/cyg_ass.h> // assertion macros | |
| 58 #include <cyg/kernel/instrmnt.h> // instrumentation | |
| 59 | |
| 60 #include <cyg/kernel/intr.hxx> // our header | |
| 61 | |
| 62 #include <cyg/kernel/sched.hxx> // scheduler | |
| 63 | |
| 64 #include <cyg/kernel/sched.inl> | |
| 65 | |
| 66 // ------------------------------------------------------------------------- | |
| 2 | 67 // Statics |
| 68 | |
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69 volatile cyg_int32 Cyg_Interrupt::disable_counter[CYGNUM_KERNEL_CPU_MAX]; |
| 2 | 70 |
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71 Cyg_SpinLock Cyg_Interrupt::interrupt_disable_spinlock CYG_INIT_PRIORITY( INTERRUPTS ); |
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72 |
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73 CYG_INTERRUPT_STATE Cyg_Interrupt::interrupt_disable_state[CYGNUM_KERNEL_CPU_MAX]; |
| 2 | 74 |
| 75 // ------------------------------------------------------------------------- | |
| 0 | 76 |
| 77 Cyg_Interrupt::Cyg_Interrupt( | |
| 78 cyg_vector vec, // Vector to attach to | |
| 79 cyg_priority pri, // Queue priority | |
| 80 CYG_ADDRWORD d, // Data pointer | |
| 81 cyg_ISR *ir, // Interrupt Service Routine | |
| 82 cyg_DSR *dr // Deferred Service Routine | |
| 83 ) | |
| 84 { | |
| 2 | 85 CYG_REPORT_FUNCTION(); |
| 86 CYG_REPORT_FUNCARG5("vector=%d, priority=%d, data=%08x, isr=%08x, " | |
| 87 "dsr=%08x", vec, pri, d, ir, dr); | |
| 88 | |
| 0 | 89 vector = vec; |
| 90 priority = pri; | |
| 91 isr = ir; | |
| 92 dsr = dr; | |
| 93 data = d; | |
| 94 | |
| 95 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
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96 |
| 0 | 97 dsr_count = 0; |
| 98 next_dsr = NULL; | |
| 99 | |
| 100 #endif | |
| 101 | |
| 102 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 103 | |
| 104 next = NULL; | |
| 105 | |
| 106 #endif | |
| 2 | 107 |
| 108 CYG_REPORT_RETURN(); | |
| 0 | 109 |
| 110 }; | |
| 111 | |
| 112 // ------------------------------------------------------------------------- | |
| 113 | |
| 114 Cyg_Interrupt::~Cyg_Interrupt() | |
| 115 { | |
| 2 | 116 CYG_REPORT_FUNCTION(); |
| 0 | 117 detach(); |
| 2 | 118 CYG_REPORT_RETURN(); |
| 0 | 119 }; |
| 120 | |
| 121 // ------------------------------------------------------------------------- | |
| 122 // DSR handling statics: | |
| 123 | |
| 124 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 125 | |
| 2 | 126 Cyg_Interrupt * |
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127 Cyg_Interrupt::dsr_table[CYGNUM_KERNEL_CPU_MAX][CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE]; |
| 0 | 128 |
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129 cyg_ucount32 Cyg_Interrupt::dsr_table_head[CYGNUM_KERNEL_CPU_MAX]; |
| 0 | 130 |
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131 volatile cyg_ucount32 Cyg_Interrupt::dsr_table_tail[CYGNUM_KERNEL_CPU_MAX]; |
| 0 | 132 |
| 133 #endif | |
| 134 | |
| 135 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 136 | |
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137 Cyg_Interrupt* volatile Cyg_Interrupt::dsr_list[CYGNUM_KERNEL_CPU_MAX]; |
| 0 | 138 |
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139 # ifdef CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO |
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140 Cyg_Interrupt* volatile Cyg_Interrupt::dsr_list_tail[CYGNUM_KERNEL_CPU_MAX]; |
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141 # endif |
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142 |
| 0 | 143 #endif |
| 144 | |
| 145 // ------------------------------------------------------------------------- | |
| 146 // Call any pending DSRs | |
| 147 | |
| 2 | 148 void |
| 149 Cyg_Interrupt::call_pending_DSRs_inner(void) | |
| 0 | 150 { |
| 151 // CYG_REPORT_FUNCTION(); | |
| 152 | |
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153 HAL_SMP_CPU_TYPE cpu = CYG_KERNEL_CPU_THIS(); |
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154 |
| 0 | 155 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE |
| 156 | |
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157 while( dsr_table_head[cpu] != dsr_table_tail[cpu] ) |
| 0 | 158 { |
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159 Cyg_Interrupt *intr = dsr_table[cpu][dsr_table_head[cpu]]; |
| 0 | 160 |
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161 dsr_table_head[cpu]++; |
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162 if( dsr_table_head[cpu] >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) |
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163 dsr_table_head[cpu] = 0; |
| 0 | 164 |
| 165 CYG_INSTRUMENT_INTR(CALL_DSR, intr->vector, 0); | |
| 166 | |
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167 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
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168 |
| 0 | 169 intr->dsr( intr->vector, 1, (CYG_ADDRWORD)intr->data ); |
| 170 } | |
| 171 | |
| 172 #endif | |
| 173 | |
| 174 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 175 | |
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176 # ifdef CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO |
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177 |
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178 cyg_uint32 old_intr; |
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179 HAL_DISABLE_INTERRUPTS(old_intr); |
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180 Cyg_Interrupt* intr = dsr_list[cpu]; |
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181 CYG_ASSERT(intr != 0, "No DSRs are pended"); |
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182 dsr_list[cpu] = 0; |
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183 dsr_list_tail[cpu] = 0; |
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184 while(true) |
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185 { |
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186 cyg_count32 count = intr->dsr_count; |
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187 Cyg_Interrupt* next = intr->next_dsr; |
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188 intr->dsr_count = 0; |
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189 intr->next_dsr = 0; |
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190 HAL_RESTORE_INTERRUPTS(old_intr); |
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191 |
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192 CYG_ASSERT(intr->dsr != 0, "No DSR defined"); |
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193 CYG_ASSERT(count > 0, "DSR posted but post count is zero"); |
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194 intr->dsr(intr->vector, count, (CYG_ADDRWORD)intr->data); |
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195 |
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196 if (!next) |
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197 break; |
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198 |
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199 intr = next; |
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200 HAL_DISABLE_INTERRUPTS(old_intr); |
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201 } |
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202 |
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203 # else // ! defined CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO |
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204 |
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205 while( dsr_list[cpu] != NULL ) |
| 0 | 206 { |
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207 Cyg_Interrupt* intr; |
| 0 | 208 cyg_uint32 old_intr; |
| 209 cyg_count32 count; | |
| 210 | |
| 211 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 212 | |
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213 intr = dsr_list[cpu]; |
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214 dsr_list[cpu] = intr->next_dsr; |
| 0 | 215 count = intr->dsr_count; |
| 216 intr->dsr_count = 0; | |
| 217 | |
| 218 HAL_RESTORE_INTERRUPTS(old_intr); | |
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219 |
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220 CYG_ASSERT( intr->dsr != NULL , "No DSR defined"); |
| 0 | 221 |
| 222 intr->dsr( intr->vector, count, (CYG_ADDRWORD)intr->data ); | |
| 223 | |
| 224 } | |
| 225 | |
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226 # endif // ! defined CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO |
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227 |
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228 #endif // defined CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST |
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229 |
| 0 | 230 }; |
| 231 | |
| 2 | 232 externC void |
| 233 cyg_interrupt_call_pending_DSRs(void) | |
| 234 { | |
| 235 Cyg_Interrupt::call_pending_DSRs_inner(); | |
| 236 } | |
| 237 | |
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238 // |
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239 // Use HAL supported function to run through the DSRs, but executing using |
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240 // the separate interrupt stack if available. This function calls back |
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241 // into this module via 'cyg_interrupt_call_pending_DSRs' above, to keep |
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242 // the whole process as general as possible. |
| 2 | 243 |
| 244 void | |
| 245 Cyg_Interrupt::call_pending_DSRs(void) | |
| 246 { | |
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247 CYG_ASSERT( Cyg_Scheduler::get_sched_lock() == 1, |
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248 "DSRs being called with sched_lock not equal to 1"); |
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249 HAL_INTERRUPT_STACK_CALL_PENDING_DSRS(); |
| 2 | 250 } |
| 251 | |
| 252 | |
| 0 | 253 // ------------------------------------------------------------------------- |
| 254 | |
| 2 | 255 void |
| 256 Cyg_Interrupt::post_dsr(void) | |
| 0 | 257 { |
| 258 // CYG_REPORT_FUNCTION(); | |
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259 HAL_SMP_CPU_TYPE cpu = CYG_KERNEL_CPU_THIS(); |
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260 |
| 0 | 261 CYG_INSTRUMENT_INTR(POST_DSR, vector, 0); |
| 262 | |
| 263 cyg_uint32 old_intr; | |
| 264 | |
| 265 // We need to disable interrupts during this part to | |
| 266 // guard against nested interrupts. | |
| 267 | |
| 268 HAL_DISABLE_INTERRUPTS(old_intr); | |
| 269 | |
| 270 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE | |
| 271 | |
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272 dsr_table[cpu][dsr_table_tail[cpu]++] = this; |
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273 if( dsr_table_tail[cpu] >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE ) |
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274 dsr_table_tail[cpu] = 0; |
| 0 | 275 |
| 276 #endif | |
| 277 | |
| 278 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST | |
| 279 | |
| 280 // Only add the interrupt to the dsr list if this is | |
| 281 // the first DSR call. | |
| 282 if( dsr_count++ == 0 ) | |
| 283 { | |
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284 # ifdef CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO |
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285 |
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286 // Add to the tail of the list. |
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287 Cyg_Interrupt* tail = dsr_list_tail[cpu]; |
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288 dsr_list_tail[cpu] = this; |
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289 if( tail ) |
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290 { |
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291 CYG_ASSERT( 0 != dsr_list[cpu] , |
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292 "DSR list is not empty but its head is 0"); |
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293 tail->next_dsr = this; |
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294 } |
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295 else |
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296 { |
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297 CYG_ASSERT( 0 == dsr_list[cpu] , |
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298 "DSR list tail is 0 but its head is not"); |
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299 dsr_list[cpu] = this; |
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300 } |
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301 |
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302 # else // ! defined CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO |
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303 |
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304 // At present DSRs are pushed onto the list and will be called |
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305 // in reverse order. We do not define the order in which DSRs |
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306 // are called, so this is acceptable. |
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307 next_dsr = dsr_list[cpu]; |
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308 dsr_list[cpu] = this; |
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309 |
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310 # endif // ! defined CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO |
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311 |
| 0 | 312 } |
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313 |
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314 #endif // defined CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST |
| 0 | 315 |
| 316 HAL_RESTORE_INTERRUPTS(old_intr); | |
| 317 }; | |
| 318 | |
| 319 // ------------------------------------------------------------------------- | |
| 2 | 320 // A C callable interface to Cyg_Interrupt::post_dsr() that can be used from |
| 321 // the HAL. | |
| 0 | 322 |
| 2 | 323 externC void |
| 324 cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj ) | |
| 325 { | |
| 326 Cyg_Interrupt* intr = (Cyg_Interrupt*) intr_obj; | |
| 327 intr->post_dsr (); | |
| 328 } | |
| 329 | |
| 330 // ------------------------------------------------------------------------- | |
| 331 | |
| 332 // FIXME: should have better name - Jifl | |
| 333 externC void | |
| 334 interrupt_end( | |
| 0 | 335 cyg_uint32 isr_ret, |
| 336 Cyg_Interrupt *intr, | |
| 337 HAL_SavedRegisters *regs | |
| 338 ) | |
| 339 { | |
| 340 // CYG_REPORT_FUNCTION(); | |
| 341 | |
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342 #ifdef CYGPKG_KERNEL_SMP_SUPPORT |
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343 Cyg_Scheduler::lock(); |
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344 #endif |
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345 |
| 2 | 346 // Sometimes we have a NULL intr object pointer. |
| 347 cyg_vector vector = (intr!=NULL)?intr->vector:0; | |
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348 |
| 2 | 349 CYG_INSTRUMENT_INTR(END, vector, isr_ret); |
| 350 | |
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351 CYG_UNUSED_PARAM( cyg_vector, vector ); // prevent compiler warning |
| 2 | 352 |
| 0 | 353 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN |
| 354 | |
| 355 // Only do this if we are in a non-chained configuration. | |
| 356 // If we are chained, then chain_isr below will do the DSR | |
| 357 // posting. | |
| 358 | |
| 2 | 359 if( isr_ret & Cyg_Interrupt::CALL_DSR && intr != NULL ) intr->post_dsr(); |
| 0 | 360 |
| 361 #endif | |
| 362 | |
| 363 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 364 | |
| 365 // If we have GDB support enabled, and there is the possibility | |
| 366 // that this thread will be context switched as a result of this | |
| 367 // interrupt, then save the pointer to the saved thread context in | |
| 368 // the thread object so that GDB can get a meaningful context to | |
| 369 // look at. | |
| 370 | |
| 371 Cyg_Scheduler::get_current_thread()->set_saved_context(regs); | |
| 372 | |
| 373 #endif | |
| 374 | |
| 375 // Now unlock the scheduler, which may also call DSRs | |
| 376 // and cause a thread switch to happen. | |
| 377 | |
| 378 Cyg_Scheduler::unlock(); | |
| 379 | |
| 380 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT | |
| 381 | |
| 382 Cyg_Scheduler::get_current_thread()->set_saved_context(0); | |
| 383 | |
| 384 #endif | |
| 385 | |
| 2 | 386 CYG_INSTRUMENT_INTR(RESTORE, vector, 0); |
| 0 | 387 } |
| 388 | |
| 389 // ------------------------------------------------------------------------- | |
| 390 // Interrupt chaining statics. | |
| 391 | |
| 392 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 393 | |
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394 Cyg_Interrupt *Cyg_Interrupt::chain_list[CYGNUM_HAL_ISR_TABLE_SIZE]; |
| 0 | 395 |
| 396 #endif | |
| 397 | |
| 398 // ------------------------------------------------------------------------- | |
| 399 // Chaining ISR inserted in HAL vector | |
| 400 | |
| 401 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 402 | |
| 2 | 403 cyg_uint32 |
| 404 Cyg_Interrupt::chain_isr(cyg_vector vector, CYG_ADDRWORD data) | |
| 0 | 405 { |
| 406 Cyg_Interrupt *p = *(Cyg_Interrupt **)data; | |
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407 register cyg_uint32 isr_ret = 0; |
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408 register cyg_uint32 isr_chain_ret = 0; |
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409 |
| 0 | 410 CYG_INSTRUMENT_INTR(CHAIN_ISR, vector, 0); |
| 411 | |
| 412 while( p != NULL ) | |
| 413 { | |
| 414 if( p->vector == vector ) | |
| 415 { | |
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416 isr_ret = p->isr(vector, p->data); |
| 0 | 417 |
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418 isr_chain_ret |= isr_ret; |
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419 |
| 2 | 420 if( isr_ret & Cyg_Interrupt::CALL_DSR ) p->post_dsr(); |
| 0 | 421 |
| 2 | 422 if( isr_ret & Cyg_Interrupt::HANDLED ) break; |
| 0 | 423 } |
| 424 | |
| 425 p = p->next; | |
| 426 } | |
| 427 | |
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428 #ifdef HAL_DEFAULT_ISR |
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429 if( (isr_chain_ret & (Cyg_Interrupt::HANDLED|Cyg_Interrupt::CALL_DSR)) == 0 ) |
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430 { |
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431 // If we finished the loop for some reason other than that an |
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432 // ISR has handled the interrupt, call any default ISR to either |
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433 // report the spurious interrupt, or do some other HAL level processing |
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434 // such as GDB interrupt detection etc. |
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435 |
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436 HAL_DEFAULT_ISR( vector, 0 ); |
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437 } |
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438 #endif |
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439 |
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440 return isr_ret & ~Cyg_Interrupt::CALL_DSR; |
| 0 | 441 } |
| 442 | |
| 443 #endif | |
| 444 | |
| 445 // ------------------------------------------------------------------------- | |
| 446 // Attach an ISR to an interrupt vector. | |
| 447 | |
| 2 | 448 void |
| 449 Cyg_Interrupt::attach(void) | |
| 0 | 450 { |
| 451 CYG_REPORT_FUNCTION(); | |
| 452 | |
| 2 | 453 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 454 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 455 |
| 456 CYG_INSTRUMENT_INTR(ATTACH, vector, 0); | |
| 457 | |
| 458 HAL_INTERRUPT_SET_LEVEL( vector, priority ); | |
| 459 | |
| 460 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 461 | |
| 462 CYG_ASSERT( next == NULL , "Cyg_Interrupt already on a list"); | |
| 463 | |
| 464 cyg_uint32 index; | |
| 465 | |
| 466 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 467 | |
| 468 if( chain_list[index] == NULL ) | |
| 469 { | |
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470 int in_use CYGBLD_ATTRIB_UNUSED; |
| 0 | 471 // First Interrupt on this chain, just assign it and register |
| 472 // the chain_isr with the HAL. | |
| 473 | |
| 474 chain_list[index] = this; | |
| 475 | |
| 2 | 476 HAL_INTERRUPT_IN_USE( vector, in_use ); |
| 477 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 0 | 478 HAL_INTERRUPT_ATTACH( vector, chain_isr, &chain_list[index], NULL ); |
| 479 } | |
| 480 else | |
| 481 { | |
| 482 // There are already interrupts chained, add this one into the | |
| 483 // chain in priority order. | |
| 484 | |
| 485 Cyg_Interrupt **p = &chain_list[index]; | |
| 486 | |
| 487 while( *p != NULL ) | |
| 488 { | |
| 489 Cyg_Interrupt *n = *p; | |
| 490 | |
| 491 if( n->priority < priority ) break; | |
| 492 | |
| 493 p = &n->next; | |
| 494 } | |
| 495 next = *p; | |
| 496 *p = this; | |
| 497 } | |
| 498 | |
| 499 #else | |
| 500 | |
| 2 | 501 { |
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502 int in_use CYGBLD_ATTRIB_UNUSED; |
| 2 | 503 |
| 504 HAL_INTERRUPT_IN_USE( vector, in_use ); | |
| 505 CYG_ASSERT( 0 == in_use, "Interrupt vector not free."); | |
| 506 | |
| 507 HAL_INTERRUPT_ATTACH( vector, isr, data, this ); | |
| 508 } | |
| 0 | 509 |
| 510 #endif | |
| 2 | 511 CYG_REPORT_RETURN(); |
| 0 | 512 } |
| 513 | |
| 514 // ------------------------------------------------------------------------- | |
| 515 // Detach the ISR from the vector | |
| 516 | |
| 2 | 517 void |
| 518 Cyg_Interrupt::detach(void) | |
| 0 | 519 { |
| 520 CYG_REPORT_FUNCTION(); | |
| 521 | |
| 2 | 522 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 523 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 524 |
| 525 CYG_INSTRUMENT_INTR(DETACH, vector, 0); | |
| 526 | |
| 527 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN | |
| 528 | |
| 529 // Remove the interrupt object from the vector chain. | |
| 530 | |
| 2 | 531 cyg_uint32 index; |
| 532 | |
| 533 HAL_TRANSLATE_VECTOR( vector, index ); | |
| 534 | |
| 535 Cyg_Interrupt **p = &chain_list[index]; | |
| 0 | 536 |
| 537 while( *p != NULL ) | |
| 538 { | |
| 539 Cyg_Interrupt *n = *p; | |
| 540 | |
| 541 if( n == this ) | |
| 542 { | |
| 543 *p = next; | |
| 544 break; | |
| 545 } | |
| 546 | |
| 547 p = &n->next; | |
| 548 } | |
| 549 | |
| 550 // If this was the last one, detach the vector. | |
| 551 | |
| 2 | 552 if( chain_list[index] == NULL ) |
| 0 | 553 HAL_INTERRUPT_DETACH( vector, chain_isr ); |
| 554 | |
| 555 #else | |
| 556 | |
| 557 HAL_INTERRUPT_DETACH( vector, isr ); | |
| 558 | |
| 559 #endif | |
| 2 | 560 |
| 561 CYG_REPORT_RETURN(); | |
| 0 | 562 |
| 563 } | |
| 564 | |
| 565 // ------------------------------------------------------------------------- | |
| 566 // Get the current service routine | |
| 567 | |
| 2 | 568 void |
| 569 Cyg_Interrupt::get_vsr(cyg_vector vector, cyg_VSR **vsr) | |
| 0 | 570 { |
| 571 CYG_REPORT_FUNCTION(); | |
| 2 | 572 CYG_REPORT_FUNCARG2("vector = %d, mem to put VSR in is at %08x", vector, |
| 573 vsr); | |
| 0 | 574 |
| 2 | 575 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 576 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 577 |
| 578 HAL_VSR_GET( vector, vsr ); | |
| 2 | 579 |
| 580 CYG_REPORT_RETURN(); | |
| 0 | 581 } |
| 582 | |
| 583 // ------------------------------------------------------------------------- | |
| 584 // Install a vector service routine | |
| 585 | |
| 2 | 586 void |
| 587 Cyg_Interrupt::set_vsr(cyg_vector vector, cyg_VSR *vsr, cyg_VSR **old) | |
| 0 | 588 { |
| 589 CYG_REPORT_FUNCTION(); | |
| 590 | |
| 2 | 591 CYG_REPORT_FUNCARG3( "vector = %d, new vsr is at %08x, mem to put " |
| 592 "old VSR in is at %08x", vector, vsr, old); | |
| 593 | |
| 0 | 594 CYG_INSTRUMENT_INTR(SET_VSR, vector, vsr); |
| 595 | |
| 2 | 596 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector"); |
| 597 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector"); | |
| 0 | 598 |
| 599 CYG_INTERRUPT_STATE old_ints; | |
| 600 | |
| 601 HAL_DISABLE_INTERRUPTS(old_ints); | |
| 602 | |
| 603 HAL_VSR_SET( vector, vsr, old ); | |
| 604 | |
| 605 HAL_RESTORE_INTERRUPTS(old_ints); | |
| 2 | 606 |
| 607 CYG_REPORT_RETURN(); | |
| 0 | 608 } |
| 609 | |
| 610 // ------------------------------------------------------------------------- | |
| 611 // Disable interrupts at the CPU | |
| 612 | |
| 613 | |
| 2 | 614 void |
| 615 Cyg_Interrupt::disable_interrupts(void) | |
| 0 | 616 { |
| 617 CYG_REPORT_FUNCTION(); | |
| 618 | |
|
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619 CYG_INSTRUMENT_INTR(DISABLE, disable_counter[CYG_KERNEL_CPU_THIS()]+1, 0); |
| 0 | 620 |
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621 HAL_SMP_CPU_TYPE cpu_this = CYG_KERNEL_CPU_THIS(); |
| 0 | 622 |
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623 // If the disable_counter is zero, disable interrupts and claim the spinlock. |
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624 |
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625 if( 0 == disable_counter[cpu_this] ) |
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626 { |
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627 // Claim the spinlock and disable interrupts. We save the original interrupt |
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628 // enable state to restore later. |
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629 interrupt_disable_spinlock.spin_intsave(&interrupt_disable_state[cpu_this]); |
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630 } |
| 0 | 631 |
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632 // Now increment our disable counter. |
| 2 | 633 |
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634 disable_counter[cpu_this]++; |
| 2 | 635 |
| 636 CYG_REPORT_RETURN(); | |
| 0 | 637 } |
| 638 | |
| 639 | |
| 640 // ------------------------------------------------------------------------- | |
| 641 // Re-enable CPU interrupts | |
| 642 | |
| 2 | 643 void |
| 644 Cyg_Interrupt::enable_interrupts(void) | |
| 0 | 645 { |
| 646 CYG_REPORT_FUNCTION(); | |
| 647 | |
|
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648 CYG_INSTRUMENT_INTR(ENABLE, disable_counter[CYG_KERNEL_CPU_THIS()], 0); |
| 2 | 649 |
|
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650 HAL_SMP_CPU_TYPE cpu_this = CYG_KERNEL_CPU_THIS(); |
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651 |
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652 CYG_ASSERT( disable_counter[cpu_this] > 0 , "Disable counter not greater than zero"); |
| 2 | 653 |
|
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654 // If the disable counter goes to zero, then release the spinlock and restore |
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655 // the previous interrupt state. |
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656 |
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657 if( --disable_counter[cpu_this] == 0 ) |
| 2 | 658 { |
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659 interrupt_disable_spinlock.clear_intsave(interrupt_disable_state[cpu_this]); |
| 2 | 660 } |
| 661 | |
| 662 CYG_REPORT_RETURN(); | |
| 0 | 663 } |
| 664 | |
| 665 // ------------------------------------------------------------------------- | |
| 666 // Mask a specific interrupt in a PIC | |
| 667 | |
| 2 | 668 void |
| 669 Cyg_Interrupt::mask_interrupt(cyg_vector vector) | |
| 0 | 670 { |
| 671 CYG_REPORT_FUNCTION(); | |
| 2 | 672 CYG_REPORT_FUNCARG1("vector=%d", vector); |
| 0 | 673 |
| 2 | 674 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 675 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 676 |
| 677 CYG_INSTRUMENT_INTR(MASK, vector, 0); | |
| 678 | |
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679 CYG_INTERRUPT_STATE old_ints; |
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680 |
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681 HAL_DISABLE_INTERRUPTS(old_ints); |
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682 HAL_INTERRUPT_MASK( vector ); |
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683 HAL_RESTORE_INTERRUPTS(old_ints); |
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684 |
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685 CYG_REPORT_RETURN(); |
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686 } |
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687 |
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688 // ------------------------------------------------------------------------- |
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689 // Mask a specific interrupt in a PIC (but not interrupt safe) |
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690 |
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691 void |
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692 Cyg_Interrupt::mask_interrupt_intunsafe(cyg_vector vector) |
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693 { |
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694 CYG_REPORT_FUNCTION(); |
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695 CYG_REPORT_FUNCARG1("vector=%d", vector); |
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696 |
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697 |
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698 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
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699 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); |
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700 |
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701 CYG_INSTRUMENT_INTR(MASK, vector, 0); |
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702 |
| 2 | 703 HAL_INTERRUPT_MASK( vector ); |
| 704 | |
| 705 CYG_REPORT_RETURN(); | |
| 0 | 706 } |
| 707 | |
| 708 // ------------------------------------------------------------------------- | |
| 709 // Clear PIC mask | |
| 710 | |
| 2 | 711 void |
| 712 Cyg_Interrupt::unmask_interrupt(cyg_vector vector) | |
| 0 | 713 { |
| 714 CYG_REPORT_FUNCTION(); | |
| 715 | |
| 2 | 716 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 717 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 718 |
| 719 CYG_INSTRUMENT_INTR(UNMASK, vector, 0); | |
| 720 | |
|
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721 CYG_INTERRUPT_STATE old_ints; |
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722 |
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723 HAL_DISABLE_INTERRUPTS(old_ints); |
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724 HAL_INTERRUPT_UNMASK( vector ); |
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725 HAL_RESTORE_INTERRUPTS(old_ints); |
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726 |
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727 CYG_REPORT_RETURN(); |
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728 } |
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729 |
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730 |
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731 // ------------------------------------------------------------------------- |
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732 // Clear PIC mask (but not interrupt safe) |
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733 |
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734 void |
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735 Cyg_Interrupt::unmask_interrupt_intunsafe(cyg_vector vector) |
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736 { |
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737 CYG_REPORT_FUNCTION(); |
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738 |
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739 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
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740 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); |
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741 |
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742 CYG_INSTRUMENT_INTR(UNMASK, vector, 0); |
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743 |
| 0 | 744 HAL_INTERRUPT_UNMASK( vector ); |
| 2 | 745 |
| 746 CYG_REPORT_RETURN(); | |
| 0 | 747 } |
| 748 | |
| 749 | |
| 750 // ------------------------------------------------------------------------- | |
| 751 // Acknowledge interrupt at PIC | |
| 752 | |
| 2 | 753 void |
| 754 Cyg_Interrupt::acknowledge_interrupt(cyg_vector vector) | |
| 0 | 755 { |
| 756 // CYG_REPORT_FUNCTION(); | |
| 757 | |
| 2 | 758 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 759 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 760 |
| 761 CYG_INSTRUMENT_INTR(ACK, vector, 0); | |
| 762 | |
| 763 HAL_INTERRUPT_ACKNOWLEDGE( vector ); | |
| 764 } | |
| 765 | |
| 766 // ------------------------------------------------------------------------- | |
| 767 // Change interrupt detection at PIC | |
| 768 | |
| 2 | 769 void |
| 770 Cyg_Interrupt::configure_interrupt( | |
| 0 | 771 cyg_vector vector, // vector to control |
| 772 cyg_bool level, // level or edge triggered | |
| 773 cyg_bool up // hi/lo level, rising/falling edge | |
| 774 ) | |
| 775 { | |
| 776 CYG_REPORT_FUNCTION(); | |
| 2 | 777 CYG_REPORT_FUNCARG3("vector = %d, level = %d, up = %d", vector, level, |
| 778 up); | |
| 0 | 779 |
| 2 | 780 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
| 781 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); | |
| 0 | 782 |
| 783 CYG_INSTRUMENT_INTR(CONFIGURE, vector, (level<<1)|up); | |
| 784 | |
| 785 HAL_INTERRUPT_CONFIGURE( vector, level, up ); | |
| 2 | 786 |
| 787 CYG_REPORT_RETURN(); | |
| 0 | 788 } |
| 789 | |
| 790 // ------------------------------------------------------------------------- | |
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791 // SMP support for setting/getting interrupt CPU |
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792 |
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793 #ifdef CYGPKG_KERNEL_SMP_SUPPORT |
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794 |
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795 void |
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796 Cyg_Interrupt::set_cpu( |
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797 cyg_vector vector, // vector to control |
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798 HAL_SMP_CPU_TYPE cpu // CPU to set |
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799 ) |
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800 { |
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801 CYG_REPORT_FUNCTION(); |
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802 CYG_REPORT_FUNCARG2("vector = %d, cpu = %d", vector, cpu ); |
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803 |
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804 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
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805 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); |
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806 |
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807 CYG_INSTRUMENT_INTR(SET_CPU, vector, cpu); |
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808 |
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809 HAL_INTERRUPT_SET_CPU( vector, cpu ); |
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810 |
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811 CYG_REPORT_RETURN(); |
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812 } |
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813 |
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814 HAL_SMP_CPU_TYPE |
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815 Cyg_Interrupt::get_cpu( |
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816 cyg_vector vector // vector to control |
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817 ) |
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818 { |
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819 CYG_REPORT_FUNCTION(); |
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820 CYG_REPORT_FUNCARG1("vector = %d", vector); |
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821 |
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822 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector"); |
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823 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector"); |
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824 |
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825 HAL_SMP_CPU_TYPE cpu = 0; |
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826 |
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827 HAL_INTERRUPT_GET_CPU( vector, cpu ); |
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828 |
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829 CYG_INSTRUMENT_INTR(GET_CPU, vector, cpu); |
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830 |
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831 CYG_REPORT_RETURN(); |
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832 |
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833 return cpu; |
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834 } |
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835 |
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836 #endif |
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837 |
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838 // ------------------------------------------------------------------------- |
| 0 | 839 // EOF intr/intr.cxx |
