| Sun, 04 Nov 2012 13:48:31 +0000 |
vae |
Define register access to FTFL module. Contributed by Nicolas Aujoux at 2012-09-07 [Bugzilla 1001561]
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| Sat, 03 Nov 2012 15:51:54 +0000 |
vae |
Separate data and code caches, as well as text indentation suggested by Jifl. Fixes to cache and SDRAM CDL and functions Improved SDRAM controller support due to better manufacturer documentation: Configurable pad control. [Bugzilla 1001606]
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| Mon, 06 Aug 2012 06:56:59 +0000 |
vae |
Add functions and macros for clock gating control to Kinetis.
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| Wed, 06 Jun 2012 19:49:59 +0000 |
vae |
Provide for cache enablement in RAM startup mode [Bugzilla 1001606]
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| Sat, 19 May 2012 10:36:22 +0000 |
jld |
* twr_k40x256/current/cdl/hal_cortexm_kinetis_twr_k40x256.cdl,
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| Fri, 18 May 2012 21:27:23 +0000 |
vae |
New files -- Kinetis variant documentation. [Bug 1001580]
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| Fri, 18 May 2012 18:32:15 +0000 |
vae |
Bug fix: Do not refer external memory if Platform startup is not selected. [ Bugzilla 1001590 ]
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| Wed, 09 May 2012 22:14:17 +0000 |
vae |
Add: Clocking support for PLL1 (K70), DDRAM controller Cache, eDMA - 32 chan. [Bugzilla 1001579
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| Fri, 30 Mar 2012 14:53:43 +0000 |
jld |
* ecos.db: Add Kinetis KwikStik platform HAL and target definition.
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| Wed, 22 Feb 2012 21:26:08 +0000 |
vae |
* cdl/kinetis_irq_scheme.cdl
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| Sun, 25 Dec 2011 13:48:16 +0000 |
vae |
Convenience macros for manipulating GPIO pins.
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| Sun, 30 Oct 2011 20:07:41 +0000 |
sergeig |
* New package -- Freescale Kinetis variant HAL.
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