flash_v2: packages/hal/powerpc/arch/current/src/vectors.S annotate

annotate packages/hal/powerpc/arch/current/src/vectors.S @ 16:4f2df4ab82c8 ecos-sw-1999-06-18

Merge from eCos master repository on 1999-06-18-15:25:04-BST

author	jlarmour
date	Fri, 18 Jun 1999 07:59:09 +0000
parents	01ce82f3e11a
children	7253dcc42a09

rev	line source
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	1 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	2 ##
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	3 ## vectors.S
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	4 ##
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	5 ## PowerPC exception vectors
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	6 ##
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	7 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	8 #####COPYRIGHTBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	9 #
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	10 # -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	11 # The contents of this file are subject to the Cygnus eCos Public License
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	12 # Version 1.0 (the "License"); you may not use this file except in
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	13 # compliance with the License. You may obtain a copy of the License at
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	14 # http://sourceware.cygnus.com/ecos
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	15 #
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	16 # Software distributed under the License is distributed on an "AS IS"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	17 # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	18 # License for the specific language governing rights and limitations under
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	19 # the License.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	20 #
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	21 # The Original Code is eCos - Embedded Cygnus Operating System, released
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	22 # September 30, 1998.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	23 #
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	24 # The Initial Developer of the Original Code is Cygnus. Portions created
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	25 # by Cygnus are Copyright (C) 1998,1999 Cygnus Solutions. All Rights Reserved.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	26 # -------------------------------------------
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	27 #
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	28 #####COPYRIGHTEND####
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	29 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	30 #######DESCRIPTIONBEGIN####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	31 ##
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	32 ## Author(s): nickg, jskov
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	33 ## Contributors: nickg, jskov
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	34 ## Date: 1999-02-20
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	35 ## Purpose: PowerPC exception vectors
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	36 ## Description: This file defines the code placed into the exception
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	37 ## vectors. It also contains the first level default VSRs
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	38 ## that save and restore state for both exceptions and
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	39 ## interrupts.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	40 ##
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	41 ######DESCRIPTIONEND####
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	42 ##
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	43 ##==========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	44
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	45 #include <pkgconf/hal.h>
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	46
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	47 #ifdef CYGPKG_KERNEL
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	48 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	49 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	50
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	51 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	52 #include "cyg/hal/ppc_regs.h"
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	53 #include "cyg/hal/ppc.inc"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	54
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	55 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	56
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	57 .file "vectors.S"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	58
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	59 .extern hal_interrupt_handlers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	60 .extern hal_interrupt_data
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	61 .extern hal_interrupt_objects
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	62
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	63 .extern cyg_instrument
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	64
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	65 .extern hal_hardware_init
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	66
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	67 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	68 # MSR initialization value
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	69 # zero all bits except:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	70 # FP = floating point available
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	71 # ME = machine check enabled
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	72 # IP = vectors at 0xFFFxxxxx (ROM startup only)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	73 # IR = instruction address translation
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	74 # DR = data address translation
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	75 # RI = recoverable interrupt
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	76
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	77 #define CYG_MSR_COMMON (MSR_FP \| MSR_ME \| MSR_IR \| MSR_DR \| MSR_RI)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	78 #if defined(CYG_HAL_STARTUP_ROM) \|\| defined(CYG_HAL_STARTUP_STUBS)
16 4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	79 # ifdef CYG_HAL_POWERPC_COPY_VECTORS
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	80 # define CYG_MSR CYG_MSR_COMMON
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	81 # else
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	82 # define CYG_MSR (CYG_MSR_COMMON \| MSR_IP)
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	83 # endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	84 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	85 #ifdef CYG_HAL_STARTUP_RAM
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	86 #define CYG_MSR CYG_MSR_COMMON
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	87 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	88 #ifdef CYG_HAL_POWERPC_SIM
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	89 # When building for SIM, don~t enable MMU -- it~s not needed since caches
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	90 # are disabled, and there is a runtime simulation overhead.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	91 #undef CYG_MSR
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	92 #define CYG_MSR (CYG_MSR_COMMON & ~(MSR_IR \| MSR_DR))
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	93 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	94
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	95 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	96 # If the following option is enabled, we only save registers up to R12.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	97 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	98 # not need to save them when calling C functions.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	99
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	100 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	101
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	102 #define MAX_SAVE_REG 12
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	103
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	104 #else
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	105
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	106 #define MAX_SAVE_REG 31
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	107
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	108 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	109
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	110 #===========================================================================
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	111 # Start by defining the exceptions vectors that must be placed at
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	112 # locations 0xFFF00000 and 0x00000000. The following code will normally
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	113 # be located at 0xFFF00000 in the ROM. It may optionally be copied out
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	114 # to 0x00000000 if we want to use the RAM vectors. For this reason this code
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	115 # MUST BE POSITION INDEPENDENT. In RAM loaded configurations, this code may
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	116 # be placed at 0x00000000 during loading.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	117
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	118 .section ".vectors","ax"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	119
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	120 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	121 # Unused first vector.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	122
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	123 rom_vectors:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	124 lwi r3,_start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	125 mtlr r3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	126 blr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	127
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	128 .byte 0x11
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	129 .byte 0x22
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	130 .byte 0x33
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	131 .byte 0x44
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	132
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	133 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	134 # Reset vector.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	135
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	136 .p2align 8
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	137 .globl reset_vector
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	138
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	139 reset_vector:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	140 lwi r3,_start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	141 mtlr r3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	142 blr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	143
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	144 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	145 # Macro for generating an exception vector service routine
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	146
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	147 .macro exception_vector name
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	148 .p2align 8
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	149 .globl __exception_\name
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	150 __exception_\name:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	151 mtspr SPRG1,r3 # stash some work registers away
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	152 mtspr SPRG2,r4
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	153 mtspr SPRG3,r5
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	154 mfcr r4 # stash CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	155 li r5,__exception_\name@L # load low half of vector address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	156 srwi r5,r5,6 # shift right by 6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	157 lwi r3,hal_vsr_table # table base
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	158 lwzx r3,r3,r5 # address of vsr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	159 mflr r5 # save link register
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	160 mtlr r3 # put vsr address into it
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	161 li r3,__exception_\name@L # reload low half of vector address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	162 blr # go to common code
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	163 .endm
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	164
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	165 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	166 # Define the exception vectors.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	167
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	168 # These are the architecture defined vectors that
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	169 # are always present.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	170
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	171 exception_vector machine_check
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	172 exception_vector data_storage
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	173 exception_vector instruction_storage
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	174 exception_vector external
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	175 exception_vector alignment
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	176 #if defined(CYG_HAL_STARTUP_ROM) \|\| defined(CYG_HAL_STARTUP_STUBS) \
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	177 \|\| defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	178 exception_vector program
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	179 #else
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	180 # Provide a crude hook to the GDB exception handler in ROM.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	181 # This allows the testing infrastructure to rely on breakpoints
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	182 # to terminate tests, even when the tests are compiled without
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	183 # the GDB stub.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	184 # It is _not_ a generic solution to the problem; in particular it
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	185 # is not possible to continue after a breakpoint is hit.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	186 .p2align 8
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	187 .globl __exception_program
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	188 __exception_program:
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	189 bl _init_CPU # disable caches.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	190 lwi r3,0xfff00700 # address of trap handler
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	191 mtlr r3 # in ROM.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	192 blr # jump to it.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	193
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	194 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	195 exception_vector floatingpoint_unavailable
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	196 exception_vector decrementer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	197 exception_vector reserved_00a00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	198 exception_vector reserved_00b00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	199 exception_vector system_call
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	200 exception_vector trace
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	201 exception_vector floatingpoint_assist
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	202 exception_vector reserved_00f00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	203
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	204 # There are some additional vectors defined
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	205 # on various implementations.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	206
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	207 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	208 # MPC8xx vectors
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	209
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	210 exception_vector software_emu
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	211 exception_vector instruction_tlb_miss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	212 exception_vector data_tlb_miss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	213 exception_vector instruction_tlb_error
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	214 exception_vector data_tlb_error
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	215 exception_vector reserved_01500
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	216 exception_vector reserved_01600
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	217 exception_vector reserved_01700
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	218 exception_vector reserved_01800
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	219 exception_vector reserved_01900
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	220 exception_vector reserved_01A00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	221 exception_vector reserved_01B00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	222 exception_vector data_breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	223 exception_vector instruction_breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	224 exception_vector peripheral_breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	225 exception_vector NMI_port
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	226
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	227 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	228 rom_vectors_end:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	229
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	230 #===========================================================================
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	231 # Real startup code. We jump here from the various reset vectors to set up
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	232 # the world.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	233
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	234 .text
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	235 .globl _start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	236
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	237 _start:
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	238 # Initialize CPU
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	239 bl _init_CPU
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	240
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	241 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	242 # Disable special MPC8xx "development support" which
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	243 # suppresses trace exceptions. The CPU seems to hang, not
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	244 # executing from offset 0x1e00(?) as expected.
16 4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	245
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	246 lwi r3,0x00000007
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	247 mtspr ICTRL,r3
4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	248
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	249 li r3,0
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	250 mtspr DER, r3
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	251 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	252
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	253 # Set up global offset table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	254 lwi r2,_GLOBAL_OFFSET_TABLE_
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	255
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	256 # set up time base register to zero
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	257 xor r3,r3,r3
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	258 mtspr TBL_W,r3
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	259 xor r4,r4,r4
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	260 mtspr TBU_W,r4
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	261
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	262 # Call platform specific hardware initialization
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	263 # This may include memory controller initialization. It is not
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	264 # safe to access RAM until after this point.
16 4f2df4ab82c8 Merge from eCos master repository on 1999-06-18-15:25:04-BST jlarmour parents: 14 diff changeset	265 bl hal_hardware_init # this is platform dependent
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	266
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	267 # set up stack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	268 lwi sp,__interrupt_stack
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	269 mtspr SPRG0,sp # save in sprg0 for later use
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	270
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	271 #if defined(CYG_HAL_STARTUP_ROM) \|\| defined(CYG_HAL_STARTUP_STUBS)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	272
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	273 # Copy data from ROM to ram
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	274 lwi r3,__rom_data_start # r3 = rom start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	275 lwi r4,__ram_data_start # r4 = ram start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	276 lwi r5,__ram_data_end # r5 = ram end
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	277
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	278 cmplw r4,r5 # skip if no data
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	279 beq 2f
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	280
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	281 1:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	282 lwz r0,0(r3) # get word from ROM
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	283 stw r0,0(r4) # store in RAM
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	284 addi r3,r3,4 # increment by 1 word
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	285 addi r4,r4,4 # increment by 1 word
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	286 cmplw r4,r5 # compare
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	287 blt 1b # loop if not yet done
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	288 2:
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	289 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	290
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	291
01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	292 #ifdef CYG_HAL_POWERPC_COPY_VECTORS // only for CygMon-supported startup
01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	293 # Copy RAM exception vectors from ROM (or load place) to RAM
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	294 lwi r3,rom_vectors # r3 = rom start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	295 lwi r4,0 # r4 = ram start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	296 lwi r5,rom_vectors_end # r5 = rom end
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	297
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	298 cmplw r3,r5 # skip if no vectors
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	299 beq 2f
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	300
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	301 1:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	302 lwz r0,0(r3) # get word from ROM
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	303 stw r0,0(r4) # store in RAM
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	304 addi r3,r3,4 # increment by 1 word
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	305 addi r4,r4,4 # increment by 1 word
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	306 cmplw r3,r5 # compare
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	307 blt 1b # loop if not yet done
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	308 2:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	309 #endif
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	310
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	311 # clear BSS
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	312 .extern __bss_start
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	313 .extern __bss_end
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	314 lwi r3,__bss_start # r3 = start
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	315 lwi r4,__bss_end # r4 = end
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	316 li r0,0 # r0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	317 cmplw r3,r4 # skip if no bss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	318 beq 2f
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	319
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	320 1: stw r0,0(r3) # store zero
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	321 addi r3,r3,4 # increment by 1 word
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	322 cmplw r3,r4 # compare
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	323 blt 1b # loop if not yet done
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	324 2:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	325
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	326 # clear SBSS
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	327 .extern __sbss_start
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	328 .extern __sbss_end
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	329 lwi r3,__sbss_start # r3 = start
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	330 lwi r4,__sbss_end # r4 = end
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	331 cmplw r3,r4 # skip if no sbss
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	332 beq 2f
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	333
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	334 1: stw r0,0(r3) # store zero
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	335 addi r3,r3,4 # increment by 1 word
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	336 cmplw r3,r4 # compare
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	337 blt 1b # loop if not yet done
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	338 2:
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	339
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	340 # It is now safe to call C functions which may rely on initialized
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	341 # data.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	342
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	343 # Set up stack for calls to C code.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	344 subi sp,sp,12 # make space on stack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	345 li r0,0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	346 stw r0,0(sp) # clear back chain
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	347 stw r0,8(sp) # zero return pc
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	348 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	349
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	350 # Initialize MMU.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	351 .extern hal_MMU_init
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	352 bl hal_MMU_init
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	353
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	354 # Enable MMU it so we can safely enable caches.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	355 lwi r3,CYG_MSR
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	356 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	357 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	358 sync
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	359
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	360 # Enable caches
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	361 .extern hal_enable_caches
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	362 bl hal_enable_caches
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	363
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	364 # call c++ constructors
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	365 .extern cyg_hal_invoke_constructors
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	366 bl cyg_hal_invoke_constructors
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	367
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	368 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	369 .extern initialize_stub
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	370 bl initialize_stub
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	371 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	372
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	373 .extern cyg_start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	374 bl cyg_start # call cyg_start
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	375 9:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	376 b 9b # if we return, loop
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	377
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	378 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	379 # This code handles the common part of all exception handlers.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	380 # It saves the machine state onto the stack and then calls
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	381 # a "C" routine to do the rest of the work. This work may result
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	382 # in thread switches, and changes to the saved state. When we return
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	383 # here the saved state is restored and execution is continued.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	384
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	385 .text
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	386
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	387 .extern __default_exception_vsr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	388 __default_exception_vsr:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	389
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	390 # We come here with all register containing their
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	391 # pre-exception values except:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	392 # R3 = ls 16 bits of vector address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	393 # R4 = saved CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	394 # R5 = saved LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	395 # LR = VSR address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	396 # SPRG1 = old R3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	397 # SPRG2 = old R4
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	398 # SPRG3 = old R5
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	399 # SRR0 = old PC
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	400 # SRR1 = old MSR and the exception cause (the POW state is lost!)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	401
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	402 subi r1,r1,ppc_exception_decrement
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	403 # leave space for registers and
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	404 # a safety margin
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	405
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	406 # First, save away some registers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	407 stw r3,ppcreg_vector(r1) # stash vector
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	408 stw r4,ppcreg_cr(r1) # stash CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	409 stw r5,ppcreg_lr(r1) # stash LR
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	410
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	411 # Enable MMU.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	412 lwi r3,CYG_MSR
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	413 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	414 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	415 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	416
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	417 mfspr r3,SPRG1 # save original R3
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	418 stw r3,ppcreg_regs+3*4(r1)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	419 mfspr r4,SPRG2 # save original R4
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	420 stw r4,ppcreg_regs+4*4(r1)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	421 mfspr r5,SPRG3 # save original R5
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	422 stw r5,ppcreg_regs+5*4(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	423
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	424 stw r0,ppcreg_regs(r1) # save R0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	425 stw r2,ppcreg_regs+2*4(r1) # save R2
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	426
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	427 mr r3,r1 # recreate original R1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	428 addi r3,r3,ppc_exception_decrement
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	429 stw r3,ppcreg_regs+1*4(r1) # and save it in state
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	430
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	431 # Save registers r6..r12/r31
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	432 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	433 .rept MAX_SAVE_REG+1-6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	434 stw _reg,(ppcreg_regs+_reg*4)(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	435 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	436 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	437
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	438 # Save registers used in vsr (r14+r15)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	439 stw r14,(ppcreg_regs+14*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	440 stw r15,(ppcreg_regs+15*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	441
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	442 # get remaining CPU registers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	443 mfxer r3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	444 mfctr r5
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	445 mfdar r6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	446 mfdsisr r7
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	447 mfpvr r8
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	448 mfsrr0 r9
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	449 mfsrr1 r10
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	450
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	451 # and store them
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	452 stw r3,ppcreg_xer(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	453 stw r5,ppcreg_ctr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	454 stw r6,ppcreg_dar(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	455 stw r7,ppcreg_dsisr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	456 stw r8,ppcreg_pvr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	457 stw r9,ppcreg_pc(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	458 stw r10,ppcreg_msr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	459
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	460 # The entire CPU state is now stashed on the stack,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	461 # call into C to do something with it.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	462
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	463 mr r3,sp # R3 = register dump
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	464
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	465 subi sp,sp,ppc_stack_frame_size # make a null frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	466
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	467 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	468 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	469 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	470
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	471 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	472 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	473
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	474 lwi r5,restore_state # get return link
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	475 mtlr r5 # to link register
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	476
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	477 .extern cyg_hal_exception_handler
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	478 b cyg_hal_exception_handler # call C code, r3 = registers
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	479
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	480 # When the call returns it will go to restore_state below.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	481
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	482
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	483 ##--------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	484 ## The following macros are defined depending on whether the Interrupt
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	485 ## system is using isr tables or chaining, and depending on the interrupt
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	486 ## controller in the system.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	487
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	488 ## Note: CYG_ISR_TABLE_SIZE must match CYG_ISR_COUNT defined in hal_intr.h.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	489
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	490 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	491
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	492 ## First level decoding of MPC8xx SIU interrupt controller.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	493
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	494 #define CYG_ISR_TABLE_SIZE 59
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	495
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	496 # decode the interrupt
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	497 .macro decode_interrupt dreg,state
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	498 lwz \dreg,ppcreg_vector(\state) # retrieve vector number,
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	499 rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	500 beq 0f # done if decrementer (vec 0)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	501 lwi \dreg,CYGARC_REG_IMM_SIVEC # if external, get SIU
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	502 lbz \dreg,0(\dreg) # vector.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	503 srwi \dreg,\dreg,2
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	504 addi \dreg,\dreg,1 # Skip decrementer vector
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	505 0: stw \dreg,ppcreg_vector(\state) # update vector in state frame.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	506 slwi \dreg,\dreg,2 # convert to byte offset.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	507 .endm
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	508
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	509 #else
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	510
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	511 ## This is the simple version. No interrupt controller, ppcreg_vector
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	512 ## is updated with the decoded interrupt vector. Isr tables/chaining
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	513 ## use same interrupt decoder.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	514 ## Bit 21 biffers between decrementer (0) and external (1).
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	515
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	516 #define CYG_ISR_TABLE_SIZE 2
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	517
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	518 # decode the interrupt
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	519 .macro decode_interrupt dreg,state
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	520 lwz \dreg,ppcreg_vector(\state) # retrieve vector number,
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	521 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	522 stw \dreg,ppcreg_vector(\state) # vector in state frame.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	523 slwi \dreg,\dreg,2 # convert to word offset.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	524 .endm
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	525
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	526 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	527
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	528 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	529 # Common interrupt handling code.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	530
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	531 .extern __default_interrupt_vsr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	532 __default_interrupt_vsr:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	533
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	534 # We come here with all register containing their
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	535 # pre-exception values except:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	536 # R3 = ls 16 bits of vector address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	537 # R4 = saved CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	538 # R5 = saved LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	539 # LR = VSR address
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	540 # SPRG1 = old R3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	541 # SPRG2 = old R4
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	542 # SPRG3 = old R5
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	543 # SRR0 = old PC
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	544 # SRR1 = old MSR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	545
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	546
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	547 subi r1,r1,ppc_exception_decrement
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	548 # leave space for registers and
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	549 # a safety margin
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	550
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	551 stw r3,ppcreg_vector(r1) # stash vector
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	552 stw r4,ppcreg_cr(r1) # stash CR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	553 stw r5,ppcreg_lr(r1) # stash LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	554
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	555 # Enable MMU.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	556 lwi r3,CYG_MSR
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	557 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	558 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	559 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	560
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	561 mfspr r3,SPRG1 # save original R3
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	562 stw r3,ppcreg_regs+3*4(r1)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	563 mfspr r4,SPRG2 # save original R4
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	564 stw r4,ppcreg_regs+4*4(r1)
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	565 mfspr r5,SPRG3 # save original R5
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	566 stw r5,ppcreg_regs+5*4(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	567
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	568 stw r0,ppcreg_regs(r1) # save R0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	569 stw r2,ppcreg_regs+2*4(r1) # save R2
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	570
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	571 mr r3,r1 # recreate original R1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	572 addi r3,r3,ppc_exception_decrement
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	573 stw r3,ppcreg_regs+1*4(r1) # and save it in state
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	574
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	575 # Save registers r6..r12/r31
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	576 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	577 .rept MAX_SAVE_REG+1-6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	578 stw _reg,(ppcreg_regs+_reg*4)(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	579 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	580 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	581
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	582 # Save registers used in vsr (r14+r15)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	583 stw r14,(ppcreg_regs+14*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	584 stw r15,(ppcreg_regs+15*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	585
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	586 # get remaining CPU registers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	587 mfxer r3
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	588 mfctr r5
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	589 mfsrr0 r6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	590 mfsrr1 r7
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	591
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	592 # and store them
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	593 stw r3,ppcreg_xer(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	594 stw r5,ppcreg_ctr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	595 stw r6,ppcreg_pc(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	596 stw r7,ppcreg_msr(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	597
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	598 # The entire CPU state is now stashed on the stack,
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	599 # increment the scheduler lock and call the ISR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	600 # for this vector.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	601
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	602 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	603 .extern cyg_scheduler_sched_lock
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	604 lwi r3,cyg_scheduler_sched_lock
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	605 lwz r4,0(r3)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	606 addi r4,r4,1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	607 stw r4,0(r3)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	608 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	609
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	610 mr r14,sp # r14 = register dump
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	611
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	612 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	613 lwi r3,__interrupt_stack # stack top
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	614 lwi r4,__interrupt_stack_base # stack base
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	615 sub. r5,sp,r4 # sp - base
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	616 blt 1f # if < 0 - not on istack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	617 sub. r5,r3,sp # top - sp
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	618 bgt 2f # if > 0 - already on istack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	619
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	620 1: mr sp,r3 # switch to istack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	621
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	622 2: stwu r14,-4(sp) # save old SP on stack
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	623
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	624 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	625
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	626 subi sp,sp,ppc_stack_frame_size # make a null frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	627
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	628 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	629 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	630 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	631
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	632 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	633 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	634
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	635 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	636
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	637 lwi r3,0x0301 # r3 = type = INTR,RAISE
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	638 lwz r4,ppcreg_vector(r14) # arg1 = vector address
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	639 srwi r4,r4,8 # arg1 = vector number
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	640 xor r5,r5,r5 # arg2 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	641 bl cyg_instrument # call instrument function
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	642
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	643 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	644
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	645 decode_interrupt r15,r14 # get table index
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	646
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	647 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	648 .extern cyg_hal_gdb_isr
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	649 lwz r3,ppcreg_pc(r14) # for serial receive irq.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	650 bl cyg_hal_gdb_isr # (arg1 is PC)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	651 cmpwi r3,0x0000 # Call ISR proper?
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	652 beq 2f # (r3 is 0 when skipping
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	653 # to avoid DSR call)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	654 1:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	655 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	656
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	657 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	658
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	659 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	660 # The CPM controller allows nested interrupts. However,
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	661 # it sits on the back of the SIU controller which has no
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	662 # HW support for this. In effect, SW masking of lower
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	663 # priority IRQs in the SIU would be required for this to work.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	664 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	665
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	666 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	667
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	668 lwz r3,ppcreg_vector(r14) # retrieve decoded vector #
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	669
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	670 lwi r6,hal_interrupt_handlers # get interrupt handler table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	671 lwzx r6,r6,r15 # load routine pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	672
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	673 lwi r4,hal_interrupt_data # get interrupt data table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	674 lwzx r4,r4,r15 # load data pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	675 # R4 = data argument
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	676
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	677 mtctr r6 # put isr address in ctr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	678
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	679 bctrl # branch to ctr reg and link
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	680
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	681 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	682 # If interrupt was caused by GDB, the ISR call above
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	683 # is skipped by jumping here.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	684 2:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	685 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	686
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	687 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	688
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	689 # If we are returning from the last nested interrupt, move back
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	690 # to the thread stack. interrupt_end() must be called on the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	691 # thread stack since it potentially causes a context switch.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	692 # Since we have arranged for the top of stack location to
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	693 # contain the sp we need to go back to here, just pop it off
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	694 # and put it in SP.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	695
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	696
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	697 lwz sp,ppc_stack_frame_size2(sp) # sp = sp
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	698
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	699 subi sp,sp,ppc_stack_frame_size # make a null frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	700
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	701 li r0,0 # R0 = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	702 stw r0,0(sp) # backchain = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	703 stw r0,8(sp) # return pc = 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	704
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	705 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	706 # where C code can save LR
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	707 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	708
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	709 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	710
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	711 # We only need to call _interrupt_end() when there is a kernel
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	712 # present to do any tidying up.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	713
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	714 # on return r3 bit 1 will indicate whether a DSR is
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	715 # to be posted. Pass this together with a pointer to
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	716 # the interrupt object we have just used to the
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	717 # interrupt tidy up routine.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	718
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	719 # Note that r14 and r15 are defined to be preserved across
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	720 # calls by the calling convention, so they still contain
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	721 # the register dump and the vector number respectively.
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	722
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	723 # Note: The instructions restoring the msr mask out the POW bit.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	724 # When eCos gets power management aware, this bit will have to be
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	725 # set to the correct state rather than just cleared.
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	726
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	727 lwi r4,hal_interrupt_objects # get interrupt object table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	728 lwzx r4,r4,r15 # load object pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	729
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	730 lwz r6,ppcreg_msr(r14) # restore msr, including
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	731 lis r5,0xfffe # interrupt enable.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	732 andc r6,r6,r5 # mask out reserved bits
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	733 sync # (and POW!)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	734 mtmsr r6
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	735 sync
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	736
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	737 mr r5,r14 # arg3 = saved register dump
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	738
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	739 .extern interrupt_end
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	740 bl interrupt_end # call into C to finish off
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	741 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	742
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	743 restore_state:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	744 # All done, restore CPU state and continue
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	745
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	746 addi sp,sp,ppc_stack_frame_size*2 # retrieve CPU state pointer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	747
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	748 # get sprs we want to restore
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	749 lwz r3,ppcreg_cr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	750 lwz r4,ppcreg_pc(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	751 lwz r5,ppcreg_msr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	752 lwz r6,ppcreg_xer(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	753 lwz r7,ppcreg_lr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	754 lwz r8,ppcreg_ctr(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	755
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	756
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	757 # stuff some of them into the CPU
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	758 mtxer r6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	759 mtlr r7
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	760 mtctr r8
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	761
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	762 # restore R0 and R2
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	763 lwz r0,ppcreg_regs(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	764 lwz r2,ppcreg_regs+2*4(sp)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	765
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	766 # Restore registers used in vsr (r14+r15)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	767 lwz r14,(ppcreg_regs+14*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	768 lwz r15,(ppcreg_regs+15*4)(r1)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	769
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	770 # restore registers r6..r12/r31
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	771 .set _reg,6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	772 .rept MAX_SAVE_REG+1-6
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	773 lwz _reg,(ppcreg_regs+_reg*4)(r1)
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	774 .set _reg,_reg+1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	775 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	776
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	777 # Here all the registers are loaded except
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	778 # r1 = ppcregs
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	779 # r3 = ccr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	780 # r4 = srr0 = pc
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	781 # r5 = srr1 = msr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	782
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	783 # We have to disable interrupts while srr0 and
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	784 # srr1 are loaded, since another interrupt will
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	785 # destroy them.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	786
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	787 mtcr r3 # set ccr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	788
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	789 lwi r3,CYG_MSR # do rest with ints disabled
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	790 sync
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	791 mtmsr r3
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	792 sync
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	793
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	794 mtsrr0 r4 # load old pc
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	795 mtsrr1 r5 # load old msr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	796
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	797 lwz r3,ppcreg_regs+3*4(r1) # load r3 value
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	798 lwz r4,ppcreg_regs+4*4(r1) # load r4 value
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	799 lwz r5,ppcreg_regs+5*4(r1) # load r5 value
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	800 lwz r1,ppcreg_regs+1*4(r1) # restore r1
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	801
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	802 sync # settle things down
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	803 isync
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	804 rfi # and return
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	805
10 d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	806
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	807
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	808 ##-----------------------------------------------------------------------------
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	809 ## Execute pending DSRs on the interrupt stack with interrupts enabled.
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	810 ## Note: this can only be called from code running on a thread stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	811
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	812 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	813 .extern cyg_interrupt_call_pending_DSRs
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	814
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	815 FUNC_START(hal_interrupt_stack_call_pending_DSRs)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	816 # Disable interrupts
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	817 mfmsr r4
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	818 lis r3,0
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	819 ori r3,r3,0x8000
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	820 andc r5,r4,r3
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	821 mtmsr r5
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	822
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	823 # Change to interrupt stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	824 mr r3,sp
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	825 lwi sp,__interrupt_stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	826 stwu r3,-4(sp) # store old stackptr on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	827 mflr r3
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	828 stwu r3,-4(sp) # store lr on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	829 stwu r4,-4(sp) # store msr values on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	830 stwu r5,-4(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	831
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	832 # Set up stack for calls to C code.
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	833 subi sp,sp,12 # make space on stack
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	834 li r0,0
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	835 stw r0,0(sp) # clear back chain
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	836 stw r0,8(sp) # zero return pc
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	837 stwu sp,-ppc_stack_frame_size(sp) # create new stack frame
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	838
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	839 # Restore interrupt state
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	840 mtmsr r4
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	841
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	842 # Call into kernel which will execute DSRs
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	843 bl cyg_interrupt_call_pending_DSRs
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	844
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	845 # Unwind stack and get msr values
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	846 lwzu r5,12+ppc_stack_frame_size(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	847 lwz r4,4(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	848 lwz r3,8(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	849 mtlr r3
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	850
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	851 # Disable interrupts
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	852 mtmsr r5
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	853
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	854 # Restore original stack pointer, original interrupt state and return
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	855 lwz sp,12(sp)
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	856 mtmsr r4
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	857
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	858 blr
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	859 #endif
d3fbcdfa1b2f Merge from eCos master repository on 1999-05-29-00:13:11-BST jlarmour parents: 8 diff changeset	860
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	861 #---------------------------------------------------------------------------
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	862 # Code for putting the CPU in a post-reset state; disabling MMU and caches.
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	863 _init_CPU:
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	864 #ifdef CYG_HAL_POWERPC_MPC8xx
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	865 lwi r3,CYGARC_REG_DC_CMD_CD
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	866 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	867 mtspr CYGARC_REG_DC_CST,r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	868 lwi r3,CYGARC_REG_IC_CMD_CD
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	869 isync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	870 mtspr CYGARC_REG_IC_CST,r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	871 isync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	872 #endif
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	873
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	874 # Set up MSR (disable MMU for now)
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	875 lwi r3,(CYG_MSR & ~(MSR_IR \| MSR_DR))
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	876 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	877 mtmsr r3
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	878 sync
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	879 blr
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	880
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	881 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	882 # This table contains a VSR pointer for each defined exception.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	883 # All of these except 5 and 9 point to the __default_exception_vsr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	884 # above, 5 and 9 point to the __default_interrupt_vsr. Entries in
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	885 # this table may be changed using Cyg_Interrupt::set_vsr().
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	886
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	887 .data
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	888
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	889 .globl hal_vsr_table
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	890 hal_vsr_table:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	891 # Architecture defined vectors
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	892 .long __default_exception_vsr # reserved
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	893 .long __default_exception_vsr # system reset
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	894 .long __default_exception_vsr # machine check
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	895 .long __default_exception_vsr # data storage
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	896 .long __default_exception_vsr # instruction storage
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	897
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	898 .long __default_interrupt_vsr # external interrupt
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	899
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	900 .long __default_exception_vsr # alignment
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	901 .long __default_exception_vsr # program
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	902 .long __default_exception_vsr # floating point unavailable
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	903
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	904 .long __default_interrupt_vsr # decrementer
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	905
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	906 .long __default_exception_vsr # reserved 0x0a00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	907 .long __default_exception_vsr # reserved 0x0b00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	908 .long __default_exception_vsr # system call
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	909 .long __default_exception_vsr # trace
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	910 .long __default_exception_vsr # floating point assist
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	911 .long __default_exception_vsr # reserved 0x0f00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	912
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	913 #ifdef CYG_HAL_POWERPC_MPC8xx
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	914
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	915 # Implementation defined vectors
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	916 .long __default_exception_vsr # software emulation
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	917 .long __default_exception_vsr # instruction TLB miss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	918 .long __default_exception_vsr # data TLB miss
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	919 .long __default_exception_vsr # instruction TLB error
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	920 .long __default_exception_vsr # data TLB error
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	921 .long __default_exception_vsr # reserved 0x1500
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	922 .long __default_exception_vsr # reserved 0x1600
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	923 .long __default_exception_vsr # reserved 0x1700
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	924 .long __default_exception_vsr # reserved 0x1800
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	925 .long __default_exception_vsr # reserved 0x1900
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	926 .long __default_exception_vsr # reserved 0x1a00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	927 .long __default_exception_vsr # reserved 0x1b00
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	928 .long __default_exception_vsr # data breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	929 .long __default_exception_vsr # instruction breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	930 .long __default_exception_vsr # peripheral breakpoint
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	931 .long __default_exception_vsr # non maskable development port
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	932 #endif
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	933
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	934 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	935 # Interrupt vector tables.
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	936 # These tables contain the isr, data and object pointers used to deliver
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	937 # interrupts to user code.
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	938
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	939 #if (CYG_ISR_TABLE_SIZE > 2)
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	940 .data
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	941 #else
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	942 .section ".sdata","aw"
443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	943 #endif
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	944
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	945 .extern hal_default_decrementer_isr
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	946 .extern hal_default_isr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	947
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	948 .globl hal_interrupt_handlers
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	949 hal_interrupt_handlers:
14 01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	950 .long hal_default_decrementer_isr
01ce82f3e11a Merge from eCos master repository on 1999-06-11-17:05:41-BST jlarmour parents: 10 diff changeset	951 .rept CYG_ISR_TABLE_SIZE-1
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	952 .long hal_default_isr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	953 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	954
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	955 .globl hal_interrupt_data
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	956 hal_interrupt_data:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	957 .rept CYG_ISR_TABLE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	958 .long 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	959 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	960
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	961 .globl hal_interrupt_objects
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	962 hal_interrupt_objects:
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	963 .rept CYG_ISR_TABLE_SIZE
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	964 .long 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	965 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	966
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	967 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	968 ## Temporary interrupt stack
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	969
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	970 .section ".bss"
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	971
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	972 .balign 16
8 ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	973 .global cyg_interrupt_stack_base
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	974 cyg_interrupt_stack_base:
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	975 __interrupt_stack_base:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	976 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	977 .byte 0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	978 .endr
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	979 .balign 16
8 ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	980 .global cyg_interrupt_stack
ece80412419a Merge from eCos master repository on 1999-05-21-22:05:54-BST jlarmour parents: 2 diff changeset	981 cyg_interrupt_stack:
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	982 __interrupt_stack:
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	983
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	984 .long 0,0,0,0,0,0,0,0
3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	985
2 443894e2e912 Block commit of eCos version 1.2.1 jlarmour parents: 0 diff changeset	986 #---------------------------------------------------------------------------
0 3111d98ba7b3 Initial commit of eCos version 1.1 jlarmour parents: diff changeset	987 # end of vectors.S

Mercurial > flash_v2

annotate packages/hal/powerpc/arch/current/src/vectors.S @ 16:4f2df4ab82c8 ecos-sw-1999-06-18