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annotate packages/hal/mips/arch/current/include/hal_arch.h @ 2729:74dbf4c3f2e1 after-copyright-change-20090129

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Update all copyright banners to reflect FSF ownership; fix and improve licence text.
author jlarmour
date Thu, 29 Jan 2009 17:47:46 +0000
parents d2c90368aeef
children 403e17f06bec
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1 #ifndef CYGONCE_HAL_HAL_ARCH_H
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2 #define CYGONCE_HAL_HAL_ARCH_H
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3
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4 //==========================================================================
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5 //
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6 // hal_arch.h
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7 //
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8 // Architecture specific abstractions
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9 //
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10 //==========================================================================
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11 // ####ECOSGPLCOPYRIGHTBEGIN####
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12 // -------------------------------------------
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13 // This file is part of eCos, the Embedded Configurable Operating System.
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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15 //
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16 // eCos is free software; you can redistribute it and/or modify it under
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17 // the terms of the GNU General Public License as published by the Free
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18 // Software Foundation; either version 2 or (at your option) any later
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19 // version.
208
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20 //
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21 // eCos is distributed in the hope that it will be useful, but WITHOUT
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22 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // for more details.
208
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25 //
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26 // You should have received a copy of the GNU General Public License
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27 // along with eCos; if not, write to the Free Software Foundation, Inc.,
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28 // 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
208
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29 //
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30 // As a special exception, if other files instantiate templates or use
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31 // macros or inline functions from this file, or you compile this file
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32 // and link it with other works to produce a work based on this file,
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33 // this file does not by itself cause the resulting work to be covered by
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34 // the GNU General Public License. However the source code for this file
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35 // must still be made available in accordance with section (3) of the GNU
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36 // General Public License v2.
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37 //
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38 // This exception does not invalidate any other reasons why a work based
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39 // on this file might be covered by the GNU General Public License.
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40 // -------------------------------------------
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41 // ####ECOSGPLCOPYRIGHTEND####
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42 //==========================================================================
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43 //#####DESCRIPTIONBEGIN####
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44 //
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45 // Author(s): nickg
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46 // Contributors: nickg, dmoseley
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47 // Date: 1999-02-17
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48 // Purpose: Define architecture abstractions
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49 // Usage: #include <cyg/hal/hal_arch.h>
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50 //
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51 //####DESCRIPTIONEND####
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52 //
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53 //==========================================================================
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55 #ifndef __ASSEMBLER__
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56 #include <pkgconf/hal.h>
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57 #include <cyg/infra/cyg_type.h>
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58
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59 #include <cyg/hal/var_arch.h>
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60
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61 //--------------------------------------------------------------------------
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62 // Processor saved states:
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63 // The layout of this structure is also defined in "arch.inc", for assembly
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64 // code. Do not change this without changing that (or vice versa).
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65 // Notes: This structure is carefully laid out. It is a multiple of 8
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66 // bytes and the pc and badvr fields are positioned to ensure that
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67 // they are on 8 byte boundaries.
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68
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69 #ifdef CYGHWR_HAL_MIPS_64BIT
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70 # define CYG_HAL_MIPS_REG CYG_WORD64
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71 # define CYG_HAL_MIPS_REG_SIZE 8
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72 #else
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73 # define CYG_HAL_MIPS_REG CYG_WORD32
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74 # define CYG_HAL_MIPS_REG_SIZE 4
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75 #endif
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76
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77 #if defined(CYGHWR_HAL_MIPS_FPU)
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78 # if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
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79 # define CYG_HAL_FPU_REG CYG_WORD64
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80 # elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
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81 # define CYG_HAL_FPU_REG CYG_WORD32
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82 # else
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83 # error MIPS FPU register size not defined
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84 # endif
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85 #endif
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86
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87 typedef struct
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88 {
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89 // These are common to all saved states
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90 CYG_HAL_MIPS_REG d[32]; /* Data regs */
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91 CYG_HAL_MIPS_REG hi; /* hi word of mpy/div reg */
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92 CYG_HAL_MIPS_REG lo; /* lo word of mpy/div reg */
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93 #ifdef CYGHWR_HAL_MIPS_FPU
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94 CYG_HAL_FPU_REG f[32]; /* FPU registers */
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95 CYG_WORD32 fcr31; /* FPU control/status register */
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96 CYG_WORD32 fppad; /* Dummy location to make this */
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97 /* structure a multiple of 8 */
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98 /* bytes long. */
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99 #endif
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100
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101 // These are only saved for exceptions and interrupts
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102 CYG_WORD32 vector; /* Vector number */
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103 CYG_WORD32 sr; /* Status Reg */
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104 CYG_HAL_MIPS_REG pc; /* Program Counter */
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105 CYG_WORD32 cache; /* Cache control register */
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106
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107
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108 // These are only saved for exceptions, and are not restored
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109 // when continued.
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110 CYG_WORD32 cause; /* Exception cause register */
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111 CYG_HAL_MIPS_REG badvr; /* Bad virtual address reg */
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112 CYG_WORD32 prid; /* Processor Version */
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113 CYG_WORD32 config; /* Config register */
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114 } HAL_SavedRegisters;
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115
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116 //--------------------------------------------------------------------------
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117 // Exception handling function.
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118 // This function is defined by the kernel according to this prototype. It is
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119 // invoked from the HAL to deal with any CPU exceptions that the HAL does
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120 // not want to deal with itself. It usually invokes the kernel's exception
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121 // delivery mechanism.
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122
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123 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
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124
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125 //--------------------------------------------------------------------------
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126 // Bit manipulation macros
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127
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128 externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
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129 externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
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130
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131 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
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132
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133 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
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134
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135 //--------------------------------------------------------------------------
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136 // Context Initialization
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137
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138
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139 // Optional FPU context initialization
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140 #ifdef CYGHWR_HAL_MIPS_FPU
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141 #define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ) \
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142 { \
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143 for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->f[_i_] = (_id_)|0xFF00|_i_; \
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144 (_regs_)->fcr31 = 0x01000000; \
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145 }
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146 #else
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147 #define HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ )
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148 #endif
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149
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150
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151 // Initialize the context of a thread.
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152 // Arguments:
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153 // _sparg_ name of variable containing current sp, will be written with new sp
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154 // _thread_ thread object address, passed as argument to entry point
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155 // _entry_ entry point address.
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156 // _id_ bit pattern used in initializing registers, for debugging.
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157 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
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158 { \
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159 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-56; \
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160 register HAL_SavedRegisters *_regs_; \
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161 int _i_; \
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162 _sp_ = _sp_ & 0xFFFFFFF0; \
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163 _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters))&0xFFFFFFF0); \
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164 for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_; \
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165 HAL_THREAD_INIT_FPU_CONTEXT( _regs_, _id_ ); \
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166 (_regs_)->d[29] = (CYG_HAL_MIPS_REG)(_sp_); /* SP = top of stack */ \
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167 (_regs_)->d[04] = (CYG_HAL_MIPS_REG)(_thread_); /* R4 = arg1 = thread ptr */ \
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168 (_regs_)->lo = 0; /* LO = 0 */ \
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169 (_regs_)->hi = 0; /* HI = 0 */ \
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170 (_regs_)->d[30] = (CYG_HAL_MIPS_REG)(_sp_); /* FP = top of stack */ \
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171 (_regs_)->d[31] = (CYG_HAL_MIPS_REG)(_entry_); /* RA(d[31]) = entry point*/ \
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172 (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = entry point */ \
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173 (_regs_)->sr = 0x00000001; /* SR = ls 3 bits only */ \
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174 _sparg_ = (CYG_ADDRESS)_regs_; \
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175 }
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176
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177 //--------------------------------------------------------------------------
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178 // Context switch macros.
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179 // The arguments are pointers to locations where the stack pointer
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180 // of the current thread is to be stored, and from where the sp of the
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181 // next thread is to be fetched.
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182
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183 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
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184 externC void hal_thread_load_context( CYG_ADDRESS to )
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185 __attribute__ ((noreturn));
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186
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187 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
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188 hal_thread_switch_context( (CYG_ADDRESS)_tspptr_, \
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189 (CYG_ADDRESS)_fspptr_);
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190
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191 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
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192 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
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193
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194 //--------------------------------------------------------------------------
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195 // Execution reorder barrier.
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196 // When optimizing the compiler can reorder code. In multithreaded systems
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197 // where the order of actions is vital, this can sometimes cause problems.
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198 // This macro may be inserted into places where reordering should not happen.
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199 // The "memory" keyword is potentially unnecessary, but it is harmless to
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200 // keep it.
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201
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202 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
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203
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204 //--------------------------------------------------------------------------
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205 // Breakpoint support
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206 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
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207 // happen if executed.
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208 // HAL_BREAKINST is the value of the breakpoint instruction and
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209 // HAL_BREAKINST_SIZE is its size in bytes.
112
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210 // HAL_BREAKINST_TYPE is the type.
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211
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212 #define HAL_BREAKPOINT(_label_) \
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213 asm volatile (" .globl " #_label_ ";" \
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214 #_label_":" \
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215 " break 5" \
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216 );
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217
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218 #define HAL_BREAKINST 0x0005000d
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219
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220 #define HAL_BREAKINST_SIZE 4
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221
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222 #define HAL_BREAKINST_TYPE cyg_uint32
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223
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224 //--------------------------------------------------------------------------
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225 // Thread register state manipulation for GDB support.
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226
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227 // Default to a 32 bit register size for GDB register dumps.
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228 #ifndef CYG_HAL_GDB_REG
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229 #define CYG_HAL_GDB_REG CYG_WORD32
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230 #endif
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231
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232 // Translate a stack pointer as saved by the thread context macros above into
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233 // a pointer to a HAL_SavedRegisters structure.
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234 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
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235 (_regs_) = (HAL_SavedRegisters *)(_sp_)
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236
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237 // If the CPU has an FPU, we also need to move the FPU registers.
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238 #ifdef CYGHWR_HAL_MIPS_FPU
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239 #define HAL_GET_GDB_FPU_REGISTERS( _regval_ , _regs_ ) \
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240 CYG_MACRO_START \
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241 int _i_; \
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242 for( _i_ = 0; _i_ < 32; _i_++ ) \
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243 _regval_[38+_i_] = (_regs_)->f[_i_]; \
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244 _regval_[70] = (_regs_)->fcr31; \
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245 CYG_MACRO_END
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246 #define HAL_SET_GDB_FPU_REGISTERS( _regs_ , _regval_ ) \
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247 CYG_MACRO_START \
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248 int _i_; \
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249 for( _i_ = 0; _i_ < 32; _i_++ ) \
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250 (_regs_)->f[_i_] = _regval_[38+_i_]; \
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251 (_regs_)->fcr31 = _regval_[70]; \
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252 CYG_MACRO_END
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253 #else
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254 #define HAL_GET_GDB_FPU_REGISTERS( _regval_ , _regs_ )
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255 #define HAL_SET_GDB_FPU_REGISTERS( _regs_ , _regval_ )
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256 #endif
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257
198
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258 // Some targets also report the state of all the coprocessor 0
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259 // registers to GDB. If that is the case then
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260 // CYGPKG_HAL_MIPS_GDB_REPORT_CP0 will be defined and the
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261 // HAL_[G|S]ET_CP0_REGISTER_*() macros will be defined.
163
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262
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263 #ifdef CYGPKG_HAL_MIPS_GDB_REPORT_CP0
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264
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265 #define HAL_GET_GDB_CP0_REGISTERS( _regval_, _regs_ ) \
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266 HAL_GET_CP0_REGISTER_32( _regval_[74], 0, 0 ); /* index */ \
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267 HAL_GET_CP0_REGISTER_32( _regval_[75], 1, 0 ); /* random */ \
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268 HAL_GET_CP0_REGISTER_32( _regval_[76], 2, 0 ); /* EntryLo0 */ \
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269 HAL_GET_CP0_REGISTER_32( _regval_[77], 3, 0 ); /* EntryLo1 */ \
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270 HAL_GET_CP0_REGISTER_64( _regval_[78], 4, 0 ); /* context */ \
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271 HAL_GET_CP0_REGISTER_32( _regval_[79], 5, 0 ); /* PageMask */ \
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272 HAL_GET_CP0_REGISTER_32( _regval_[80], 6, 0 ); /* Wired */ \
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273 (_regval_)[81] = 0xC0C0C006; \
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274 (_regval_)[82] = (_regs_)->badvr; /* BadVr */ \
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275 HAL_GET_CP0_REGISTER_32( _regval_[83], 9, 0 ); /* Count */ \
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276 HAL_GET_CP0_REGISTER_64( _regval_[84], 10, 0 ); /* EntryHi */ \
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277 HAL_GET_CP0_REGISTER_32( _regval_[85], 11, 0 ); /* Compare */ \
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278 (_regval_)[86] = (_regs_)->sr; /* Status */ \
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279 (_regval_)[87] = (_regs_)->cause; /* Cause */ \
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280 HAL_GET_CP0_REGISTER_64( _regval_[88], 14, 0 ); /* EPC */ \
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281 HAL_GET_CP0_REGISTER_32( _regval_[89], 15, 0 ); /* PRId */ \
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282 HAL_GET_CP0_REGISTER_32( _regval_[90], 16, 0 ); /* Config */ \
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283 HAL_GET_CP0_REGISTER_32( _regval_[91], 17, 0 ); /* LLAddr */ \
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284 HAL_GET_CP0_REGISTER_64( _regval_[92], 18, 0 ); /* WatchLo */ \
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285 HAL_GET_CP0_REGISTER_32( _regval_[93], 19, 0 ); /* WatchHi */ \
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286 HAL_GET_CP0_REGISTER_64( _regval_[94], 20, 0 ); /* XContext */ \
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287 (_regval_)[95] = 0xC0C0C021; \
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288 (_regval_)[96] = 0xC0C0C022; \
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289 HAL_GET_CP0_REGISTER_32( _regval_[97], 23, 0 ); /* Debug */ \
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290 HAL_GET_CP0_REGISTER_64( _regval_[98], 24, 0 ); /* DEPC */ \
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291 (_regval_)[99] = 0xC0C0C025; \
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292 HAL_GET_CP0_REGISTER_32( _regval_[100], 26, 0 ); /* ErrCtl */ \
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293 HAL_GET_CP0_REGISTER_32( _regval_[101], 27, 0 ); /* CacheErr */ \
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294 HAL_GET_CP0_REGISTER_32( _regval_[102], 28, 0 ); /* TagLo */ \
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295 HAL_GET_CP0_REGISTER_32( _regval_[103], 29, 0 ); /* TagHi */ \
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296 HAL_GET_CP0_REGISTER_64( _regval_[104], 30, 0 ); /* ErrorEPC */ \
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297 HAL_GET_CP0_REGISTER_64( _regval_[105], 31, 0 ); /* DESAVE */ \
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298 HAL_GET_CP0_REGISTER_32( _regval_[106], 16, 1 ); /* Config1 */
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299
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300 #define HAL_SET_GDB_CP0_REGISTERS( _regval_, _regs_ ) \
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301 HAL_SET_CP0_REGISTER_32( _regval_[74], 0, 0 ); /* index */ \
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302 HAL_SET_CP0_REGISTER_32( _regval_[76], 2, 0 ); /* EntryLo0 */ \
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303 HAL_SET_CP0_REGISTER_32( _regval_[77], 3, 0 ); /* EntryLo1 */ \
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304 HAL_SET_CP0_REGISTER_64( _regval_[78], 4, 0 ); /* context */ \
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305 HAL_SET_CP0_REGISTER_32( _regval_[79], 5, 0 ); /* PageMask */ \
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306 HAL_SET_CP0_REGISTER_32( _regval_[80], 6, 0 ); /* Wired */ \
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307 HAL_SET_CP0_REGISTER_32( _regval_[83], 9, 0 ); /* Count */ \
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308 HAL_SET_CP0_REGISTER_64( _regval_[84], 10, 0 ); /* EntryHi */ \
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309 HAL_SET_CP0_REGISTER_32( _regval_[85], 11, 0 ); /* Compare */ \
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310 HAL_SET_CP0_REGISTER_32( _regval_[90], 16, 0 ); /* Config */ \
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311 HAL_SET_CP0_REGISTER_64( _regval_[92], 18, 0 ); /* WatchLo */ \
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312 HAL_SET_CP0_REGISTER_32( _regval_[93], 19, 0 ); /* WatchHi */ \
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313 HAL_SET_CP0_REGISTER_64( _regval_[94], 20, 0 ); /* XContext */ \
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314 HAL_SET_CP0_REGISTER_32( _regval_[97], 23, 0 ); /* Debug */ \
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315 HAL_SET_CP0_REGISTER_64( _regval_[98], 24, 0 ); /* DEPC */ \
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316 HAL_SET_CP0_REGISTER_32( _regval_[100], 26, 0 ); /* ErrCtl */ \
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317 HAL_SET_CP0_REGISTER_32( _regval_[101], 27, 0 ); /* CacheErr */ \
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318 HAL_SET_CP0_REGISTER_32( _regval_[102], 28, 0 ); /* TagLo */ \
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319 HAL_SET_CP0_REGISTER_32( _regval_[103], 29, 0 ); /* TagHi */ \
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320 HAL_SET_CP0_REGISTER_64( _regval_[105], 31, 0 ); /* DESAVE */
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321
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322 #else
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323 #define HAL_GET_GDB_CP0_REGISTERS( _regval_, _regs_ )
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324 #define HAL_SET_GDB_CP0_REGISTERS( _regval_, _regs_ )
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325 #endif
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326
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327 // Copy a set of registers from a HAL_SavedRegisters structure into a
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328 // GDB ordered array.
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329 #define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \
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330 { \
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331 CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
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332 int _i_; \
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333 \
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334 for( _i_ = 0; _i_ < 32; _i_++ ) \
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335 _regval_[_i_] = (_regs_)->d[_i_]; \
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336 \
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337 HAL_GET_GDB_FPU_REGISTERS( _regval_, _regs_ ); \
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338 \
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339 _regval_[32] = (_regs_)->sr; \
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340 _regval_[33] = (_regs_)->lo; \
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341 _regval_[34] = (_regs_)->hi; \
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342 _regval_[35] = (_regs_)->badvr; \
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343 _regval_[36] = (_regs_)->cause; \
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344 _regval_[37] = (_regs_)->pc; \
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345 \
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346 HAL_GET_GDB_CP0_REGISTERS( _regval_, _regs_ ); \
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347 }
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348
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349 // Copy a GDB ordered array into a HAL_SavedRegisters structure.
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350 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
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351 { \
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352 CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
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353 int _i_; \
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354 \
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355 for( _i_ = 0; _i_ < 32; _i_++ ) \
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356 (_regs_)->d[_i_] = _regval_[_i_]; \
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357 \
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358 HAL_SET_GDB_FPU_REGISTERS( _regs_, _regval_ ); \
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359 \
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360 (_regs_)->sr = _regval_[32]; \
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361 (_regs_)->lo = _regval_[33]; \
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362 (_regs_)->hi = _regval_[34]; \
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363 (_regs_)->badvr = _regval_[35]; \
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364 (_regs_)->cause = _regval_[36]; \
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365 (_regs_)->pc = _regval_[37]; \
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366 \
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367 HAL_SET_GDB_CP0_REGISTERS( _regval_, _regs_ ); \
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368 }
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369
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370 //--------------------------------------------------------------------------
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371 // HAL setjmp
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372 // Note: These definitions are repeated in hal_arch.h. If changes are
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373 // required remember to update both sets.
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374
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375 #define CYGARC_JMP_BUF_SP 0
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376 #define CYGARC_JMP_BUF_R16 1
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377 #define CYGARC_JMP_BUF_R17 2
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378 #define CYGARC_JMP_BUF_R18 3
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379 #define CYGARC_JMP_BUF_R19 4
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380 #define CYGARC_JMP_BUF_R20 5
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381 #define CYGARC_JMP_BUF_R21 6
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382 #define CYGARC_JMP_BUF_R22 7
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383 #define CYGARC_JMP_BUF_R23 8
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384 #define CYGARC_JMP_BUF_R28 9
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385 #define CYGARC_JMP_BUF_R30 10
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386 #define CYGARC_JMP_BUF_R31 11
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387
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388 #define CYGARC_JMP_BUF_SIZE 12
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389
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390 typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
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391
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392 externC int hal_setjmp(hal_jmp_buf env);
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393 externC void hal_longjmp(hal_jmp_buf env, int val);
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394
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395 //-------------------------------------------------------------------------
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396 // Idle thread code.
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397 // This macro is called in the idle thread loop, and gives the HAL the
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398 // chance to insert code. Typical idle thread behaviour might be to halt the
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399 // processor.
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400
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401 externC void hal_idle_thread_action(cyg_uint32 loop_count);
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402
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403 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
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404
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405 //--------------------------------------------------------------------------
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406 // Minimal and sensible stack sizes: the intention is that applications
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407 // will use these to provide a stack size in the first instance prior to
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408 // proper analysis. Idle thread stack should be this big.
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409
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410 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
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411 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
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412 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
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413
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414 // This is not a config option because it should not be adjusted except
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415 // under "enough rope" sort of disclaimers.
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416
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417 // Typical case stack frame size: return link + 4 pushed registers + some locals.
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418 #define CYGNUM_HAL_STACK_FRAME_SIZE (48)
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419
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420 // Stack needed for a context switch:
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421 #if defined(CYGHWR_HAL_MIPS_FPU)
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422 # if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
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423 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*CYG_HAL_MIPS_REG_SIZE)+(32*8))
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424 # elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
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425 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*CYG_HAL_MIPS_REG_SIZE)+(32*4))
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426 # else
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427 # error MIPS FPU register size not defined
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428 # endif
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429 #else
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430 #define CYGNUM_HAL_STACK_CONTEXT_SIZE ((32+10)*CYG_HAL_MIPS_REG_SIZE)
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431 #endif
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432
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433
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434
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435 // Interrupt + call to ISR, interrupt_end() and the DSR
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436 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE)
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437
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438 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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439
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440 // An interrupt stack which is large enough for all possible interrupt
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441 // conditions (and only used for that purpose) exists. "User" stacks
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442 // can be much smaller
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443
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444 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \
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445 CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \
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446 CYGNUM_HAL_STACK_FRAME_SIZE*8)
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447 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (CYGNUM_HAL_STACK_SIZE_MINIMUM+1024)
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448
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449 #else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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450
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451 // No separate interrupt stack exists. Make sure all threads contain
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452 // a stack sufficiently large.
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453
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454 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096)
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455 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096)
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456
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457 #endif
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458
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459 #endif /* __ASSEMBLER__ */
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460
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461 // Convenience macros for accessing memory cached or uncached
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462 #define CYGARC_KSEG_MASK (0xE0000000)
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463 #define CYGARC_KSEG_CACHED (0x80000000)
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464 #define CYGARC_KSEG_UNCACHED (0xA0000000)
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465 #define CYGARC_KSEG_CACHED_BASE (0x80000000)
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466 #define CYGARC_KSEG_UNCACHED_BASE (0xA0000000)
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467 #ifndef __ASSEMBLER__
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468 #define CYGARC_CACHED_ADDRESS(x) ((((CYG_ADDRESS)(x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_CACHED)
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469 #define CYGARC_UNCACHED_ADDRESS(x) ((((CYG_ADDRESS)(x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_UNCACHED)
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470 #define CYGARC_PHYSICAL_ADDRESS(x) (((CYG_ADDRESS)(x)) & ~CYGARC_KSEG_MASK)
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471 #else // __ASSEMBLER__
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472 #define CYGARC_CACHED_ADDRESS(x) ((((x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_CACHED)
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473 #define CYGARC_UNCACHED_ADDRESS(x) ((((x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_UNCACHED)
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474 #define CYGARC_PHYSICAL_ADDRESS(x) (((x)) & ~CYGARC_KSEG_MASK)
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475 #define CYGARC_ADDRESS_REG_CACHED(reg) \
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476 and reg, reg, ~CYGARC_KSEG_MASK; \
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477 or reg, reg, CYGARC_KSEG_CACHED
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478 #define CYGARC_ADDRESS_REG_UNCACHED(reg) \
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479 and reg, reg, ~CYGARC_KSEG_MASK; \
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480 or reg, reg, CYGARC_KSEG_UNCACHED
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481 #endif /* __ASSEMBLER__ */
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482
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483 //--------------------------------------------------------------------------
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484 // Macros for switching context between two eCos instances (jump from
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485 // code in ROM to code in RAM or vice versa).
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486 #define CYGARC_HAL_SAVE_GP() \
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487 CYG_MACRO_START \
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488 register CYG_ADDRWORD __gp_save; \
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489 asm volatile ( "move %0,$28;" \
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490 ".extern _gp;" \
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491 "la $gp,_gp;" \
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492 : "=r"(__gp_save))
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493
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494 #define CYGARC_HAL_RESTORE_GP() \
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495 asm volatile ( "move $gp,%0;" :: "r"(__gp_save) ); \
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496 CYG_MACRO_END
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497
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498
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499 //--------------------------------------------------------------------------
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500 // Macro for finding return address.
200
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501 #define CYGARC_HAL_GET_RETURN_ADDRESS(_x_, _dummy_) \
101
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502 asm volatile ( "move %0,$31;" : "=r" (_x_) )
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503
200
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504 #define CYGARC_HAL_GET_RETURN_ADDRESS_BACKUP(_dummy_)
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505
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506 //--------------------------------------------------------------------------
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507 #endif // CYGONCE_HAL_HAL_ARCH_H
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508 // End of hal_arch.h