Mercurial > flash_v2
annotate packages/hal/powerpc/arch/current/src/vectors.S @ 423:d175f4be3ab6
Support for application profiling.
| author | gthomas |
|---|---|
| date | Thu, 14 Nov 2002 23:36:48 +0000 |
| parents | d2c90368aeef |
| children | 87f3e026b015 |
| rev | line source |
|---|---|
| 2 | 1 ##========================================================================== |
| 0 | 2 ## |
| 3 ## vectors.S | |
| 4 ## | |
| 5 ## PowerPC exception vectors | |
| 6 ## | |
| 2 | 7 ##========================================================================== |
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8 #####ECOSGPLCOPYRIGHTBEGIN#### |
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9 ## ------------------------------------------- |
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10 ## This file is part of eCos, the Embedded Configurable Operating System. |
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
| 423 | 12 ## Copyright (C) 2002 Gary Thomas |
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13 ## |
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14 ## eCos is free software; you can redistribute it and/or modify it under |
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15 ## the terms of the GNU General Public License as published by the Free |
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16 ## Software Foundation; either version 2 or (at your option) any later version. |
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17 ## |
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18 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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19 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 ## for more details. |
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22 ## |
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23 ## You should have received a copy of the GNU General Public License along |
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24 ## with eCos; if not, write to the Free Software Foundation, Inc., |
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25 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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26 ## |
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27 ## As a special exception, if other files instantiate templates or use macros |
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28 ## or inline functions from this file, or you compile this file and link it |
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29 ## with other works to produce a work based on this file, this file does not |
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30 ## by itself cause the resulting work to be covered by the GNU General Public |
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31 ## License. However the source code for this file must still be made available |
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32 ## in accordance with section (3) of the GNU General Public License. |
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33 ## |
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34 ## This exception does not invalidate any other reasons why a work based on |
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35 ## this file might be covered by the GNU General Public License. |
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36 ## |
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37 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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38 ## at http://sources.redhat.com/ecos/ecos-license/ |
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39 ## ------------------------------------------- |
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40 #####ECOSGPLCOPYRIGHTEND#### |
| 2 | 41 ##========================================================================== |
| 0 | 42 #######DESCRIPTIONBEGIN#### |
| 43 ## | |
| 2 | 44 ## Author(s): nickg, jskov |
| 45 ## Contributors: nickg, jskov | |
| 46 ## Date: 1999-02-20 | |
| 47 ## Purpose: PowerPC exception vectors | |
| 48 ## Description: This file defines the code placed into the exception | |
| 49 ## vectors. It also contains the first level default VSRs | |
| 50 ## that save and restore state for both exceptions and | |
| 51 ## interrupts. | |
| 0 | 52 ## |
| 53 ######DESCRIPTIONEND#### | |
| 54 ## | |
| 2 | 55 ##========================================================================== |
| 0 | 56 |
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57 #=========================================================================== |
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58 # |
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59 # The PowerPC exception handling has changed as of version 1.3.1. |
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60 # The primary motivation for rewriting the code was to bring it more |
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61 # in line with the other HALs, in particular to allow a RAM application |
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62 # to cleanly take over only a subset of vectors from a running ROM |
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63 # monitor. |
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64 # |
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65 # GDB stubs (and CygMon, should it be ported to PPC) copies |
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66 # exception vector entry handler code to address 0. These vector entry |
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67 # handlers (defined by the exception_vector macro below) compute |
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68 # a vector index into the hal_vsr_table, fetch the pointer, and |
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69 # jump to the HAL vector service routine (VSR). |
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70 # |
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71 # The hal_vsr_table is located immediately after the vector |
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72 # handlers (at address 0x3000), allowing RAM applications to |
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73 # change VSRs as necessary, while still keeping desired ROM |
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74 # monitor functionality available for debugging. |
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75 # |
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76 # ROM applications can still be configured to leave the vector entry |
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77 # handlers at 0xff000000, but there is at the moment no |
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78 # provision for reclaiming the reserved vector space in RAM to |
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79 # application usage. |
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80 # |
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81 # RAM applications can also be configured to provide exception |
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82 # handlers which are copied to address 0 on startup, thus taking |
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83 # full control of the target. |
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84 # |
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85 # |
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86 # Default configuration is for RAM applications to rely on an |
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87 # existing ROM monitor to provide debugging functionality, and |
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88 # for ROM applications to copy vectors to address 0. |
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89 # |
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90 # |
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91 # Unfortunately the new exception scheme is not compatible with the |
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92 # old scheme. Stubs and applications must be compiled using the same |
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93 # scheme (i.e., old binaries will not run with new stubs, and new |
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94 # binaries will not run with old stubs). |
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95 # |
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96 #=========================================================================== |
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97 |
| 0 | 98 #include <pkgconf/hal.h> |
| 99 | |
| 100 #ifdef CYGPKG_KERNEL | |
| 101 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT | |
| 102 #endif | |
| 2 | 103 |
| 104 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS | |
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105 #include <cyg/hal/ppc_regs.h> |
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106 |
| 2 | 107 #=========================================================================== |
| 0 | 108 |
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109 // .file "vectors.S" |
| 0 | 110 |
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111 .extern hal_interrupt_data |
| 0 | 112 .extern hal_interrupt_handlers |
| 113 .extern hal_interrupt_objects | |
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114 .extern hal_vsr_table |
| 0 | 115 |
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116 .extern cyg_hal_invoke_constructors |
| 0 | 117 .extern cyg_instrument |
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118 .extern cyg_start |
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119 .extern hal_IRQ_init |
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120 .extern hal_MMU_init |
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121 .extern hal_enable_caches |
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122 .extern hal_hardware_init |
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123 .extern initialize_stub |
| 0 | 124 |
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125 .extern __bss_start |
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126 .extern __bss_end |
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127 .extern __sbss_start |
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128 .extern __sbss_end |
| 0 | 129 |
| 2 | 130 #=========================================================================== |
| 0 | 131 # MSR initialization value |
| 132 # zero all bits except: | |
| 133 # FP = floating point available | |
| 134 # ME = machine check enabled | |
| 135 # IP = vectors at 0xFFFxxxxx (ROM startup only) | |
| 2 | 136 # IR = instruction address translation |
| 137 # DR = data address translation | |
| 0 | 138 # RI = recoverable interrupt |
| 139 | |
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140 #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_RI) |
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141 |
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142 #if (CYGHWR_HAL_POWERPC_VECTOR_BASE == 0xfff00000) |
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143 # define IP_BIT MSR_IP |
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144 #else |
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145 # define IP_BIT 0 |
| 0 | 146 #endif |
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147 |
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148 #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU |
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149 # define IR_DR_BITS (MSR_IR | MSR_DR) |
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150 #else |
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151 # define IR_DR_BITS 0 |
| 0 | 152 #endif |
| 153 | |
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154 #define CYG_MSR (CYG_MSR_COMMON | IP_BIT | IR_DR_BITS) |
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155 |
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156 # Include variant macros after MSR definition. |
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157 #include <cyg/hal/arch.inc> |
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158 #include <cyg/hal/ppc_offsets.inc> |
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159 |
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160 |
| 2 | 161 #=========================================================================== |
| 0 | 162 # If the following option is enabled, we only save registers up to R12. |
| 163 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do | |
| 164 # not need to save them when calling C functions. | |
| 165 | |
| 166 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT | |
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167 # define MAX_SAVE_REG 12 |
| 0 | 168 #else |
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169 # define MAX_SAVE_REG 31 |
| 0 | 170 #endif |
| 171 | |
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172 |
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173 #if defined(CYGHWR_HAL_POWERPC_NEED_VECTORS) |
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174 |
| 2 | 175 #=========================================================================== |
| 0 | 176 # Start by defining the exceptions vectors that must be placed at |
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177 # locations 0xFFF00000 or 0x00000000. The following code will normally |
| 0 | 178 # be located at 0xFFF00000 in the ROM. It may optionally be copied out |
| 179 # to 0x00000000 if we want to use the RAM vectors. For this reason this code | |
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180 # MUST BE POSITION INDEPENDENT. |
| 0 | 181 |
| 182 .section ".vectors","ax" | |
| 183 | |
| 2 | 184 #--------------------------------------------------------------------------- |
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185 # Macros for generating an exception vector service routine |
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186 |
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187 # Reset vector macro |
| 0 | 188 |
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189 .macro reset_vector name |
| 0 | 190 .p2align 8 |
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191 .globl __exception_\name |
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192 __exception_\name: |
| 0 | 193 lwi r3,_start |
| 194 mtlr r3 | |
| 195 blr | |
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196 .endm |
| 0 | 197 |
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198 # Generic vector macro |
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199 |
| 0 | 200 .macro exception_vector name |
| 201 .p2align 8 | |
| 202 .globl __exception_\name | |
| 203 __exception_\name: | |
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204 mtspr SPRG1,r3 # stash some work registers away |
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205 mtspr SPRG2,r4 |
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206 mtspr SPRG3,r5 |
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207 mfcr r4 # stash CR |
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208 li r5,__exception_\name-rom_vectors # load low half of vector addr |
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209 srwi r5,r5,6 # shift right by 6 |
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210 lwi r3,hal_vsr_table # table base |
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211 lwzx r3,r3,r5 # address of vsr |
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212 mflr r5 # save link register |
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213 mtlr r3 # put vsr address into it |
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214 li r3,__exception_\name-rom_vectors # reload low half of vector addr |
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215 blr # go to common code |
| 0 | 216 .endm |
| 217 | |
| 2 | 218 #--------------------------------------------------------------------------- |
| 0 | 219 # Define the exception vectors. |
| 220 | |
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221 // Some platforms won't let us put the vector code just where we want |
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222 // This macro introduces some lattitude in vector placement |
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223 |
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224 #ifdef CYG_HAL_FUDGE_VECTOR_ALIGNMENT |
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225 hal_fudge_vector_alignment |
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226 #endif |
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227 |
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228 rom_vectors: |
| 0 | 229 # These are the architecture defined vectors that |
| 230 # are always present. | |
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231 #ifdef CYG_HAL_RESERVED_VECTOR_00000 |
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232 hal_reserved_vector_00000 |
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233 #else |
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234 exception_vector reserved_00000 |
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235 #endif |
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236 reset_vector reset |
| 0 | 237 exception_vector machine_check |
| 238 exception_vector data_storage | |
| 239 exception_vector instruction_storage | |
| 240 exception_vector external | |
| 241 exception_vector alignment | |
| 242 exception_vector program | |
| 243 exception_vector floatingpoint_unavailable | |
| 244 exception_vector decrementer | |
| 245 exception_vector reserved_00a00 | |
| 246 exception_vector reserved_00b00 | |
| 247 exception_vector system_call | |
| 248 exception_vector trace | |
| 249 exception_vector floatingpoint_assist | |
| 250 exception_vector reserved_00f00 | |
| 251 | |
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252 # Variants may define extra vectors. |
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253 hal_extra_vectors |
| 0 | 254 |
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255 rom_vectors_end: |
| 0 | 256 |
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257 #else // CYGHWR_HAL_POWERPC_NEED_VECTORS |
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258 |
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259 # When vectors are not included this is the primary entry point. |
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260 .globl __exception_reset |
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261 __exception_reset: |
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262 lwi r3,_start |
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263 mtlr r3 |
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264 blr |
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265 |
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266 #endif // CYGHWR_HAL_POWERPC_NEED_VECTORS |
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267 |
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268 |
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269 |
| 2 | 270 #=========================================================================== |
| 271 # Real startup code. We jump here from the various reset vectors to set up | |
| 272 # the world. | |
| 0 | 273 |
| 274 .text | |
| 275 .globl _start | |
| 2 | 276 _start: |
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277 # Initialize CPU to a post-reset state, ensuring the ground doesn''t |
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278 # shift under us while we try to set things up. |
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279 hal_cpu_init |
| 0 | 280 |
| 281 # Set up global offset table | |
| 282 lwi r2,_GLOBAL_OFFSET_TABLE_ | |
| 283 | |
| 284 # set up time base register to zero | |
| 285 xor r3,r3,r3 | |
| 2 | 286 mtspr TBL_W,r3 |
| 0 | 287 xor r4,r4,r4 |
| 2 | 288 mtspr TBU_W,r4 |
| 289 | |
| 290 # Call platform specific hardware initialization | |
| 291 # This may include memory controller initialization. It is not | |
| 292 # safe to access RAM until after this point. | |
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293 bl hal_hardware_init # this is platform dependent |
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294 .globl _hal_hardware_init_done |
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295 _hal_hardware_init_done: |
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296 |
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297 #if !defined(CYG_HAL_STARTUP_ROM) && defined(CYGSEM_HAL_POWERPC_COPY_VECTORS) |
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298 lwi r3,rom_vectors-4 |
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299 lwi r4,(CYGHWR_HAL_POWERPC_VECTOR_BASE - 4) |
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300 lwi r5,rom_vectors_end-4 |
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301 0: lwzu r0,4(r3) |
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302 stwu r0,4(r4) |
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303 cmplw r3,r5 |
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304 bne 0b |
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305 #endif |
| 0 | 306 |
| 307 # set up stack | |
| 308 lwi sp,__interrupt_stack | |
| 2 | 309 mtspr SPRG0,sp # save in sprg0 for later use |
| 0 | 310 |
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311 # Set up exception handlers and VSR table, taking care not to |
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312 # step on any ROM monitor''s toes. |
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313 hal_mon_init |
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314 |
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315 #if defined(CYG_HAL_STARTUP_ROM) |
| 0 | 316 |
| 317 # Copy data from ROM to ram | |
| 318 lwi r3,__rom_data_start # r3 = rom start | |
| 319 lwi r4,__ram_data_start # r4 = ram start | |
| 320 lwi r5,__ram_data_end # r5 = ram end | |
| 321 | |
| 322 cmplw r4,r5 # skip if no data | |
| 323 beq 2f | |
| 324 | |
| 325 1: | |
| 326 lwz r0,0(r3) # get word from ROM | |
| 327 stw r0,0(r4) # store in RAM | |
| 328 addi r3,r3,4 # increment by 1 word | |
| 329 addi r4,r4,4 # increment by 1 word | |
| 330 cmplw r4,r5 # compare | |
| 331 blt 1b # loop if not yet done | |
| 332 2: | |
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333 #endif |
| 2 | 334 |
| 0 | 335 # clear BSS |
| 336 lwi r3,__bss_start # r3 = start | |
| 2 | 337 lwi r4,__bss_end # r4 = end |
| 0 | 338 li r0,0 # r0 = 0 |
| 339 cmplw r3,r4 # skip if no bss | |
| 340 beq 2f | |
| 341 | |
| 2 | 342 1: stw r0,0(r3) # store zero |
| 0 | 343 addi r3,r3,4 # increment by 1 word |
| 344 cmplw r3,r4 # compare | |
| 345 blt 1b # loop if not yet done | |
| 346 2: | |
| 347 | |
| 2 | 348 # clear SBSS |
| 349 lwi r3,__sbss_start # r3 = start | |
| 350 lwi r4,__sbss_end # r4 = end | |
| 351 cmplw r3,r4 # skip if no sbss | |
| 352 beq 2f | |
| 353 | |
| 354 1: stw r0,0(r3) # store zero | |
| 355 addi r3,r3,4 # increment by 1 word | |
| 356 cmplw r3,r4 # compare | |
| 357 blt 1b # loop if not yet done | |
| 358 2: | |
| 359 | |
| 360 # It is now safe to call C functions which may rely on initialized | |
| 361 # data. | |
| 362 | |
| 363 # Set up stack for calls to C code. | |
| 0 | 364 subi sp,sp,12 # make space on stack |
| 365 li r0,0 | |
| 366 stw r0,0(sp) # clear back chain | |
| 367 stw r0,8(sp) # zero return pc | |
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368 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 2 | 369 |
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370 # Variant HALs may need to do something special before we continue |
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371 bl hal_variant_init |
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372 |
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373 # Platform initialization |
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374 bl hal_platform_init |
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375 |
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376 # MMU and cache are controlled by the same option since caching |
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377 # on the PPC does not make sense without the MMU to mark regions |
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378 # which should not be cached. |
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379 #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU |
| 2 | 380 # Initialize MMU. |
| 381 bl hal_MMU_init | |
| 382 | |
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383 # Enable MMU so we can safely enable caches. |
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384 lwi r3,CYG_MSR # interrupts enabled later |
| 2 | 385 sync |
| 386 mtmsr r3 | |
| 387 sync | |
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388 |
| 2 | 389 # Enable caches |
| 390 bl hal_enable_caches | |
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391 #endif // CYGHWR_HAL_POWERPC_ENABLE_MMU |
| 0 | 392 |
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393 # set up platform specific interrupt environment |
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394 bl hal_IRQ_init |
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395 |
| 2 | 396 # call c++ constructors |
| 397 bl cyg_hal_invoke_constructors | |
| 0 | 398 |
| 2 | 399 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
| 400 bl initialize_stub | |
| 0 | 401 #endif |
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402 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ |
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403 || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) |
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404 .extern hal_ctrlc_isr_init |
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405 bl hal_ctrlc_isr_init |
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406 #endif |
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407 |
| 0 | 408 bl cyg_start # call cyg_start |
| 409 9: | |
| 410 b 9b # if we return, loop | |
| 411 | |
| 2 | 412 #--------------------------------------------------------------------------- |
| 0 | 413 # This code handles the common part of all exception handlers. |
| 414 # It saves the machine state onto the stack and then calls | |
| 415 # a "C" routine to do the rest of the work. This work may result | |
| 416 # in thread switches, and changes to the saved state. When we return | |
| 417 # here the saved state is restored and execution is continued. | |
| 418 | |
| 419 .text | |
| 420 | |
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421 .globl cyg_hal_default_exception_vsr |
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422 cyg_hal_default_exception_vsr: |
| 0 | 423 |
| 424 # We come here with all register containing their | |
| 425 # pre-exception values except: | |
| 426 # R3 = ls 16 bits of vector address | |
| 427 # R4 = saved CR | |
| 428 # R5 = saved LR | |
| 429 # LR = VSR address | |
| 430 # SPRG1 = old R3 | |
| 431 # SPRG2 = old R4 | |
| 432 # SPRG3 = old R5 | |
| 433 # SRR0 = old PC | |
| 2 | 434 # SRR1 = old MSR and the exception cause (the POW state is lost!) |
| 0 | 435 |
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436 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT |
| 0 | 437 # leave space for registers and |
| 438 # a safety margin | |
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439 #ifdef CYGPKG_HAL_POWERPC_PPC40x |
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440 // The caches on this processor are always enabled when the MMU is on |
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441 // (and disabled when off). Thus we need to be careful about cache |
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442 // polution and staleness when changing the MMU state. |
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443 // At this point, the MMU is off due to the exception. We need to |
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444 // flush the part of the cache which may be touched before the MMU |
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445 // is reenabled so that memory will be consistent when that happens. |
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446 // Of course, this is complicated by the fact that there are no "free" |
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447 // registers at this point in the code. |
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448 dcbf 0,sp // Flushes first line |
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449 stw r3,0(sp) // This is now safe |
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450 li r3,CYGARC_PPCREG_VECTOR // Flush lines which will be changed |
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451 dcbf r3,sp |
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452 li r3,CYGARC_PPCREG_CR |
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453 dcbf r3,sp |
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454 li r3,CYGARC_PPCREG_LR |
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455 dcbf r3,sp |
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456 lwz r3,0(sp) // Restore register |
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457 #endif |
| 0 | 458 |
| 459 # First, save away some registers | |
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460 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector |
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461 stw r4,CYGARC_PPCREG_CR(sp) # stash CR |
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462 stw r5,CYGARC_PPCREG_LR(sp) # stash LR |
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463 |
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464 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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465 # Mark this fram as an Exception frame |
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466 lwi r3,0xDDDDDDE0 |
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467 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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468 lwi r3,0xDDDDDDE1 |
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469 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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470 #endif |
| 2 | 471 |
| 472 # Enable MMU. | |
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473 lwi r3,CYG_MSR |
| 2 | 474 sync |
| 475 mtmsr r3 | |
| 476 sync | |
| 477 | |
| 478 mfspr r3,SPRG1 # save original R3 | |
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479 stw r3,CYGARC_PPCREG_REGS+3*4(sp) |
| 2 | 480 mfspr r4,SPRG2 # save original R4 |
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481 stw r4,CYGARC_PPCREG_REGS+4*4(sp) |
| 2 | 482 mfspr r5,SPRG3 # save original R5 |
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483 stw r5,CYGARC_PPCREG_REGS+5*4(sp) |
| 0 | 484 |
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485 stw r0,CYGARC_PPCREG_REGS+0*4(sp) # save R0 |
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486 stw r2,CYGARC_PPCREG_REGS+2*4(sp) # save R2 |
| 0 | 487 |
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488 mr r3,sp # recreate original SP |
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489 addi r3,r3,CYGARC_PPC_EXCEPTION_DECREMENT |
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490 stw r3,CYGARC_PPCREG_REGS+1*4(sp) # and save it in state |
| 0 | 491 |
| 2 | 492 # Save registers r6..r12/r31 |
| 0 | 493 .set _reg,6 |
| 494 .rept MAX_SAVE_REG+1-6 | |
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495 stw _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 496 .set _reg,_reg+1 |
| 497 .endr | |
| 498 | |
| 2 | 499 # Save registers used in vsr (r14+r15) |
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500 stw r14,(CYGARC_PPCREG_REGS+14*4)(sp) |
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501 stw r15,(CYGARC_PPCREG_REGS+15*4)(sp) |
| 2 | 502 |
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503 # get remaining family CPU registers |
| 0 | 504 mfxer r3 |
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505 mfctr r4 |
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506 mfsrr0 r5 |
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507 mfsrr1 r6 |
| 0 | 508 # and store them |
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509 stw r3,CYGARC_PPCREG_XER(sp) |
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510 stw r4,CYGARC_PPCREG_CTR(sp) |
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511 stw r5,CYGARC_PPCREG_PC(sp) |
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512 stw r6,CYGARC_PPCREG_MSR(sp) |
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513 |
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514 # Save variant registers |
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515 hal_variant_save sp |
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516 |
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517 # Save FPU registers |
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518 hal_fpu_save sp |
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519 |
| 0 | 520 # The entire CPU state is now stashed on the stack, |
| 521 # call into C to do something with it. | |
| 522 | |
| 523 mr r3,sp # R3 = register dump | |
| 524 | |
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525 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 526 |
| 527 li r0,0 # R0 = 0 | |
| 528 stw r0,0(sp) # backchain = 0 | |
| 529 stw r0,8(sp) # return pc = 0 | |
| 530 | |
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531 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 532 # where C code can save LR |
| 533 | |
| 534 lwi r5,restore_state # get return link | |
| 535 mtlr r5 # to link register | |
| 536 | |
| 2 | 537 .extern cyg_hal_exception_handler |
| 538 b cyg_hal_exception_handler # call C code, r3 = registers | |
| 0 | 539 |
| 540 # When the call returns it will go to restore_state below. | |
| 541 | |
| 542 | |
| 2 | 543 ##-------------------------------------------------------------------------- |
| 544 ## The following macros are defined depending on whether the Interrupt | |
| 545 ## system is using isr tables or chaining, and depending on the interrupt | |
| 546 ## controller in the system. | |
| 547 | |
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548 #ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED |
| 2 | 549 |
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550 ## This is the simple version. No interrupt controller, CYGARC_PPCREG_VECTOR |
| 2 | 551 ## is updated with the decoded interrupt vector. Isr tables/chaining |
| 552 ## use same interrupt decoder. | |
| 553 ## Bit 21 biffers between decrementer (0) and external (1). | |
| 554 | |
| 555 # decode the interrupt | |
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556 .macro hal_intc_decode dreg,state |
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557 lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number, |
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558 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update |
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559 stw \dreg,CYGARC_PPCREG_VECTOR(\state) # vector in state frame. |
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560 slwi \dreg,\dreg,2 # convert to word offset. |
| 2 | 561 .endm |
| 562 | |
|
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563 #endif // CYGPKG_HAL_POWERPC_INTC_DEFINED |
| 2 | 564 |
| 565 #--------------------------------------------------------------------------- | |
| 0 | 566 # Common interrupt handling code. |
| 567 | |
|
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568 .globl cyg_hal_default_interrupt_vsr |
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569 cyg_hal_default_interrupt_vsr: |
| 0 | 570 |
| 571 # We come here with all register containing their | |
| 572 # pre-exception values except: | |
| 573 # R3 = ls 16 bits of vector address | |
| 574 # R4 = saved CR | |
| 575 # R5 = saved LR | |
| 576 # LR = VSR address | |
| 577 # SPRG1 = old R3 | |
| 578 # SPRG2 = old R4 | |
| 579 # SPRG3 = old R5 | |
| 580 # SRR0 = old PC | |
| 581 # SRR1 = old MSR | |
| 582 | |
| 583 | |
|
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584 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT |
| 0 | 585 # leave space for registers and |
| 586 # a safety margin | |
|
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587 #ifdef CYGPKG_HAL_POWERPC_PPC40x |
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588 // The caches on this processor are always enabled when the MMU is on |
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589 // (and disabled when off). Thus we need to be careful about cache |
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590 // polution and staleness when changing the MMU state. |
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591 // At this point, the MMU is off due to the exception. We need to |
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592 // flush the part of the cache which may be touched before the MMU |
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593 // is reenabled so that memory will be consistent when that happens. |
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594 // Of course, this is complicated by the fact that there are no "free" |
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595 // registers at this point in the code. |
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596 dcbf 0,sp // Flushes first line |
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597 stw r3,0(sp) // This is now safe |
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598 li r3,CYGARC_PPCREG_VECTOR // Flush lines which will be changed |
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599 dcbf r3,sp |
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600 li r3,CYGARC_PPCREG_CR |
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601 dcbf r3,sp |
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602 li r3,CYGARC_PPCREG_LR |
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603 dcbf r3,sp |
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604 lwz r3,0(sp) // Restore register |
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605 #endif |
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606 |
|
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607 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector |
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608 stw r4,CYGARC_PPCREG_CR(sp) # stash CR |
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609 stw r5,CYGARC_PPCREG_LR(sp) # stash LR |
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610 |
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611 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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612 # Mark this fram as an 1nterrupt frame |
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613 lwi r3,0xDDDDDD10 |
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614 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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615 lwi r3,0xDDDDDD11 |
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616 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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617 #endif |
| 0 | 618 |
| 2 | 619 # Enable MMU. |
|
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620 lwi r3,CYG_MSR |
| 2 | 621 sync |
| 622 mtmsr r3 | |
| 623 sync | |
| 624 | |
| 625 mfspr r3,SPRG1 # save original R3 | |
|
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626 stw r3,CYGARC_PPCREG_REGS+3*4(sp) |
| 2 | 627 mfspr r4,SPRG2 # save original R4 |
|
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628 stw r4,CYGARC_PPCREG_REGS+4*4(sp) |
| 2 | 629 mfspr r5,SPRG3 # save original R5 |
|
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630 stw r5,CYGARC_PPCREG_REGS+5*4(sp) |
| 0 | 631 |
|
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632 stw r0,CYGARC_PPCREG_REGS+0*4(sp) # save R0 |
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633 stw r2,CYGARC_PPCREG_REGS+2*4(sp) # save R2 |
| 0 | 634 |
|
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635 mr r3,sp # recreate original SP |
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636 addi r3,r3,CYGARC_PPC_EXCEPTION_DECREMENT |
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637 stw r3,CYGARC_PPCREG_REGS+1*4(sp) # and save it in state |
| 0 | 638 |
| 2 | 639 # Save registers r6..r12/r31 |
| 0 | 640 .set _reg,6 |
| 641 .rept MAX_SAVE_REG+1-6 | |
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642 stw _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 643 .set _reg,_reg+1 |
| 644 .endr | |
| 645 | |
| 2 | 646 # Save registers used in vsr (r14+r15) |
|
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647 stw r14,CYGARC_PPCREG_REGS+14*4(sp) |
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648 stw r15,CYGARC_PPCREG_REGS+15*4(sp) |
| 2 | 649 |
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650 # get remaining family CPU registers |
| 0 | 651 mfxer r3 |
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652 mfctr r4 |
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653 mfsrr0 r5 |
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654 mfsrr1 r6 |
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655 |
| 0 | 656 # and store them |
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657 stw r3,CYGARC_PPCREG_XER(sp) |
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658 stw r4,CYGARC_PPCREG_CTR(sp) |
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659 stw r5,CYGARC_PPCREG_PC(sp) |
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660 stw r6,CYGARC_PPCREG_MSR(sp) |
| 0 | 661 |
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662 # Save variant registers |
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663 hal_variant_save sp |
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664 |
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665 # Save FPU registers |
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666 hal_fpu_save sp |
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667 |
| 0 | 668 # The entire CPU state is now stashed on the stack, |
| 669 # increment the scheduler lock and call the ISR | |
| 670 # for this vector. | |
| 671 | |
| 672 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 2 | 673 .extern cyg_scheduler_sched_lock |
| 674 lwi r3,cyg_scheduler_sched_lock | |
| 0 | 675 lwz r4,0(r3) |
| 676 addi r4,r4,1 | |
| 677 stw r4,0(r3) | |
| 678 #endif | |
| 679 | |
| 2 | 680 mr r14,sp # r14 = register dump |
| 0 | 681 |
| 682 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 683 lwi r3,__interrupt_stack # stack top | |
| 684 lwi r4,__interrupt_stack_base # stack base | |
| 685 sub. r5,sp,r4 # sp - base | |
| 686 blt 1f # if < 0 - not on istack | |
| 687 sub. r5,r3,sp # top - sp | |
| 688 bgt 2f # if > 0 - already on istack | |
| 689 | |
| 690 1: mr sp,r3 # switch to istack | |
| 691 | |
| 2 | 692 2: stwu r14,-4(sp) # save old SP on stack |
| 0 | 693 |
| 694 #endif | |
| 695 | |
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696 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 697 |
| 698 li r0,0 # R0 = 0 | |
| 699 stw r0,0(sp) # backchain = 0 | |
| 700 stw r0,8(sp) # return pc = 0 | |
| 701 | |
|
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702 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 703 # where C code can save LR |
| 704 | |
| 705 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 706 | |
| 707 lwi r3,0x0301 # r3 = type = INTR,RAISE | |
|
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708 lwz r4,CYGARC_PPCREG_VECTOR(r14) # arg1 = vector address |
| 0 | 709 srwi r4,r4,8 # arg1 = vector number |
| 710 xor r5,r5,r5 # arg2 = 0 | |
| 711 bl cyg_instrument # call instrument function | |
| 712 | |
| 713 #endif | |
| 714 | |
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715 hal_intc_decode r15,r14 # get table index |
| 2 | 716 |
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717 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ |
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718 || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) |
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719 # If we are supporting Ctrl-C interrupts from GDB, we must squirrel |
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720 # away a pointer to the save interrupt state here so that we can |
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721 # plant a breakpoint at some later time. |
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722 |
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723 .extern hal_saved_interrupt_state |
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724 lwi r3,hal_saved_interrupt_state |
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725 stw r14,0(r3) |
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726 |
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727 #endif |
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728 |
| 2 | 729 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING |
| 0 | 730 |
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731 #ifdef CYGPKG_HAL_POWERPC_MPC8xx |
| 2 | 732 # The CPM controller allows nested interrupts. However, |
| 733 # it sits on the back of the SIU controller which has no | |
| 734 # HW support for this. In effect, SW masking of lower | |
| 735 # priority IRQs in the SIU would be required for this to work. | |
| 736 #endif | |
| 737 | |
| 738 #endif | |
| 739 | |
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740 lwz r3,CYGARC_PPCREG_VECTOR(r14) # retrieve decoded vector # |
| 0 | 741 |
| 742 lwi r6,hal_interrupt_handlers # get interrupt handler table | |
| 743 lwzx r6,r6,r15 # load routine pointer | |
| 744 | |
| 745 lwi r4,hal_interrupt_data # get interrupt data table | |
| 746 lwzx r4,r4,r15 # load data pointer | |
| 747 # R4 = data argument | |
| 423 | 748 mr r5,r14 # R5 = saved registers |
| 0 | 749 |
| 750 mtctr r6 # put isr address in ctr | |
| 751 | |
| 752 bctrl # branch to ctr reg and link | |
| 753 | |
| 754 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 755 | |
| 756 # If we are returning from the last nested interrupt, move back | |
| 757 # to the thread stack. interrupt_end() must be called on the | |
| 758 # thread stack since it potentially causes a context switch. | |
| 759 # Since we have arranged for the top of stack location to | |
| 760 # contain the sp we need to go back to here, just pop it off | |
| 761 # and put it in SP. | |
| 762 | |
| 763 | |
|
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764 lwz sp,CYGARC_PPC_STACK_FRAME_SIZE*2(sp) # sp = *sp |
| 0 | 765 |
|
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766 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 767 |
| 768 li r0,0 # R0 = 0 | |
| 769 stw r0,0(sp) # backchain = 0 | |
| 770 stw r0,8(sp) # return pc = 0 | |
| 771 | |
|
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772 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 773 # where C code can save LR |
| 774 #endif | |
| 775 | |
| 776 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 777 | |
| 778 # We only need to call _interrupt_end() when there is a kernel | |
| 779 # present to do any tidying up. | |
| 780 | |
| 781 # on return r3 bit 1 will indicate whether a DSR is | |
| 782 # to be posted. Pass this together with a pointer to | |
| 783 # the interrupt object we have just used to the | |
| 784 # interrupt tidy up routine. | |
| 785 | |
| 2 | 786 # Note that r14 and r15 are defined to be preserved across |
| 0 | 787 # calls by the calling convention, so they still contain |
| 788 # the register dump and the vector number respectively. | |
| 2 | 789 |
| 0 | 790 lwi r4,hal_interrupt_objects # get interrupt object table |
| 791 lwzx r4,r4,r15 # load object pointer | |
|
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792 mr r5,r14 # arg3 = saved register dump |
| 0 | 793 |
| 794 .extern interrupt_end | |
| 795 bl interrupt_end # call into C to finish off | |
| 796 #endif | |
| 797 | |
| 798 restore_state: | |
| 799 # All done, restore CPU state and continue | |
| 800 | |
|
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801 # retrieve CPU state pointer |
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802 addi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE*2 |
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803 |
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804 # Restore FPU registers |
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805 hal_fpu_load sp |
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806 |
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807 # Restore variant registers |
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808 hal_variant_load sp |
| 0 | 809 |
| 810 # get sprs we want to restore | |
|
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811 # stuff some of them into the CPU |
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812 lwz r3,CYGARC_PPCREG_XER(sp) |
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813 lwz r4,CYGARC_PPCREG_LR(sp) |
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814 lwz r5,CYGARC_PPCREG_CTR(sp) |
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815 mtxer r3 |
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816 mtlr r4 |
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817 mtctr r5 |
| 0 | 818 |
| 2 | 819 # Restore registers used in vsr (r14+r15) |
|
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820 lwz r14,CYGARC_PPCREG_REGS+14*4(r1) |
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821 lwz r15,CYGARC_PPCREG_REGS+15*4(r1) |
| 2 | 822 |
| 823 # restore registers r6..r12/r31 | |
| 0 | 824 .set _reg,6 |
| 825 .rept MAX_SAVE_REG+1-6 | |
|
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826 lwz _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 827 .set _reg,_reg+1 |
| 828 .endr | |
| 829 | |
|
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830 hal_cpu_int_disable |
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831 |
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832 # restore R0 and R2 |
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833 lwz r0,CYGARC_PPCREG_REGS+0*4(sp) |
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834 lwz r2,CYGARC_PPCREG_REGS+2*4(sp) |
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835 |
| 0 | 836 # Here all the registers are loaded except |
|
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837 # sp = HAL_SavedRegisters |
| 0 | 838 # r3 = ccr |
| 839 # r4 = srr0 = pc | |
| 840 # r5 = srr1 = msr | |
|
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841 # |
| 0 | 842 # We have to disable interrupts while srr0 and |
| 843 # srr1 are loaded, since another interrupt will | |
| 844 # destroy them. | |
| 845 | |
|
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846 lwz r3,CYGARC_PPCREG_CR(sp) |
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847 lwz r4,CYGARC_PPCREG_PC(sp) |
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848 lwz r5,CYGARC_PPCREG_MSR(sp) |
| 0 | 849 mtcr r3 # set ccr |
| 850 mtsrr0 r4 # load old pc | |
| 851 mtsrr1 r5 # load old msr | |
| 852 | |
|
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853 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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854 # Mark this frame as (almost) dead. |
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855 lwi r3,0xDDDDDDD0 |
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856 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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857 lwi r3,0xDDDDDDD1 |
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858 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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859 #endif |
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860 |
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861 lwz r3,CYGARC_PPCREG_REGS+3*4(sp) # load r3 value |
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862 lwz r4,CYGARC_PPCREG_REGS+4*4(sp) # load r4 value |
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863 lwz r5,CYGARC_PPCREG_REGS+5*4(sp) # load r5 value |
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864 lwz sp,CYGARC_PPCREG_REGS+1*4(sp) # restore sp |
| 0 | 865 |
| 866 sync # settle things down | |
| 867 isync | |
| 868 rfi # and return | |
| 869 | |
|
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870 |
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871 |
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872 ##----------------------------------------------------------------------------- |
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873 ## Execute pending DSRs on the interrupt stack with interrupts enabled. |
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874 ## Note: this can only be called from code running on a thread stack |
|
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875 |
|
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876 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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877 .extern cyg_interrupt_call_pending_DSRs |
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878 |
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879 FUNC_START(hal_interrupt_stack_call_pending_DSRs) |
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880 # Change to interrupt stack, save state and set up stack for |
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881 # calls to C code. |
|
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882 mr r3,sp |
|
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883 lwi r4,__interrupt_stack |
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884 subi r4,r4,24 # make space on stack |
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885 mr sp,r4 |
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886 stw r3,12(sp) # save old sp |
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887 mfmsr r3 |
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888 stw r3,16(sp) # save old MSR |
|
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889 mflr r3 |
|
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890 stw r3,20(sp) # save old LR |
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891 |
|
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892 li r0,0 |
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893 stw r0,0(sp) # clear back chain |
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894 stw r0,8(sp) # zero return pc |
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895 |
|
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896 hal_cpu_int_enable |
|
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897 |
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898 # Call into kernel which will execute DSRs |
|
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899 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) |
|
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900 bl cyg_interrupt_call_pending_DSRs |
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901 addi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE |
|
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902 |
|
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903 lwz r3,20(sp) # restore LR |
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904 mtlr r3 |
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905 lwz r5,12(sp) # get SP from saved state |
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906 lwz r3,16(sp) # restore interrupt setting |
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907 hal_cpu_int_merge r3 |
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908 |
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909 mr sp,r5 # restore stack pointer |
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910 blr # and return to caller |
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911 #endif |
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912 |
| 2 | 913 #--------------------------------------------------------------------------- |
| 0 | 914 ## Temporary interrupt stack |
| 915 | |
| 916 .section ".bss" | |
| 917 | |
| 918 .balign 16 | |
|
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919 .global cyg_interrupt_stack_base |
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920 cyg_interrupt_stack_base: |
| 0 | 921 __interrupt_stack_base: |
| 922 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 923 .byte 0 | |
| 924 .endr | |
| 925 .balign 16 | |
|
8
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
926 .global cyg_interrupt_stack |
|
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
927 cyg_interrupt_stack: |
| 0 | 928 __interrupt_stack: |
| 929 | |
| 930 .long 0,0,0,0,0,0,0,0 | |
| 931 | |
| 2 | 932 #--------------------------------------------------------------------------- |
| 0 | 933 # end of vectors.S |