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annotate packages/hal/powerpc/arch/current/src/vectors.S @ 1777:c16341b1bac6 default tip
* Added execute permissions to files missed in conversion from CVS
| author | alexs |
|---|---|
| date | Mon, 12 Oct 2009 02:26:09 +0100 |
| parents | 3e87cf3554ba |
| children |
| rev | line source |
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| 2 | 1 ##========================================================================== |
| 0 | 2 ## |
| 3 ## vectors.S | |
| 4 ## | |
| 5 ## PowerPC exception vectors | |
| 6 ## | |
| 2 | 7 ##========================================================================== |
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8 #####ECOSGPLCOPYRIGHTBEGIN#### |
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9 ## ------------------------------------------- |
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10 ## This file is part of eCos, the Embedded Configurable Operating System. |
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11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
| 423 | 12 ## Copyright (C) 2002 Gary Thomas |
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13 ## |
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14 ## eCos is free software; you can redistribute it and/or modify it under |
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15 ## the terms of the GNU General Public License as published by the Free |
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16 ## Software Foundation; either version 2 or (at your option) any later version. |
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17 ## |
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18 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
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19 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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21 ## for more details. |
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22 ## |
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23 ## You should have received a copy of the GNU General Public License along |
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24 ## with eCos; if not, write to the Free Software Foundation, Inc., |
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25 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
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26 ## |
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27 ## As a special exception, if other files instantiate templates or use macros |
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28 ## or inline functions from this file, or you compile this file and link it |
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29 ## with other works to produce a work based on this file, this file does not |
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30 ## by itself cause the resulting work to be covered by the GNU General Public |
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31 ## License. However the source code for this file must still be made available |
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32 ## in accordance with section (3) of the GNU General Public License. |
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33 ## |
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34 ## This exception does not invalidate any other reasons why a work based on |
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35 ## this file might be covered by the GNU General Public License. |
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36 ## |
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37 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
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38 ## at http://sources.redhat.com/ecos/ecos-license/ |
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39 ## ------------------------------------------- |
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40 #####ECOSGPLCOPYRIGHTEND#### |
| 2 | 41 ##========================================================================== |
| 0 | 42 #######DESCRIPTIONBEGIN#### |
| 43 ## | |
| 2 | 44 ## Author(s): nickg, jskov |
| 45 ## Contributors: nickg, jskov | |
| 46 ## Date: 1999-02-20 | |
| 47 ## Purpose: PowerPC exception vectors | |
| 48 ## Description: This file defines the code placed into the exception | |
| 49 ## vectors. It also contains the first level default VSRs | |
| 50 ## that save and restore state for both exceptions and | |
| 51 ## interrupts. | |
| 0 | 52 ## |
| 53 ######DESCRIPTIONEND#### | |
| 54 ## | |
| 2 | 55 ##========================================================================== |
| 0 | 56 |
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57 #=========================================================================== |
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58 # |
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59 # The PowerPC exception handling has changed as of version 1.3.1. |
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60 # The primary motivation for rewriting the code was to bring it more |
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61 # in line with the other HALs, in particular to allow a RAM application |
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62 # to cleanly take over only a subset of vectors from a running ROM |
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63 # monitor. |
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64 # |
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65 # GDB stubs (and CygMon, should it be ported to PPC) copies |
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66 # exception vector entry handler code to address 0. These vector entry |
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67 # handlers (defined by the exception_vector macro below) compute |
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68 # a vector index into the hal_vsr_table, fetch the pointer, and |
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69 # jump to the HAL vector service routine (VSR). |
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70 # |
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71 # The hal_vsr_table is located immediately after the vector |
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72 # handlers (at address 0x3000), allowing RAM applications to |
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73 # change VSRs as necessary, while still keeping desired ROM |
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74 # monitor functionality available for debugging. |
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75 # |
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76 # ROM applications can still be configured to leave the vector entry |
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77 # handlers at 0xff000000, but there is at the moment no |
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78 # provision for reclaiming the reserved vector space in RAM to |
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79 # application usage. |
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80 # |
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81 # RAM applications can also be configured to provide exception |
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82 # handlers which are copied to address 0 on startup, thus taking |
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83 # full control of the target. |
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84 # |
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85 # |
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86 # Default configuration is for RAM applications to rely on an |
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87 # existing ROM monitor to provide debugging functionality, and |
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88 # for ROM applications to copy vectors to address 0. |
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89 # |
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90 # |
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91 # Unfortunately the new exception scheme is not compatible with the |
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92 # old scheme. Stubs and applications must be compiled using the same |
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93 # scheme (i.e., old binaries will not run with new stubs, and new |
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94 # binaries will not run with old stubs). |
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95 # |
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96 #=========================================================================== |
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97 |
| 0 | 98 #include <pkgconf/hal.h> |
| 99 | |
| 100 #ifdef CYGPKG_KERNEL | |
| 101 #include <pkgconf/kernel.h> // CYGPKG_KERNEL_INSTRUMENT | |
| 102 #endif | |
| 2 | 103 |
| 104 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS | |
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105 #include <cyg/hal/ppc_regs.h> |
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106 |
| 2 | 107 #=========================================================================== |
| 0 | 108 |
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109 // .file "vectors.S" |
| 0 | 110 |
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111 .extern hal_interrupt_data |
| 0 | 112 .extern hal_interrupt_handlers |
| 113 .extern hal_interrupt_objects | |
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114 .extern hal_vsr_table |
| 0 | 115 |
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116 .extern cyg_hal_invoke_constructors |
| 0 | 117 .extern cyg_instrument |
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118 .extern cyg_start |
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119 .extern hal_IRQ_init |
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120 .extern hal_MMU_init |
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121 .extern hal_enable_caches |
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122 .extern hal_hardware_init |
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123 .extern initialize_stub |
| 0 | 124 |
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125 .extern __bss_start |
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126 .extern __bss_end |
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127 .extern __sbss_start |
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128 .extern __sbss_end |
| 0 | 129 |
| 2 | 130 #=========================================================================== |
| 0 | 131 # MSR initialization value |
| 132 # zero all bits except: | |
| 133 # FP = floating point available | |
| 134 # ME = machine check enabled | |
| 135 # IP = vectors at 0xFFFxxxxx (ROM startup only) | |
| 2 | 136 # IR = instruction address translation |
| 137 # DR = data address translation | |
| 0 | 138 # RI = recoverable interrupt |
| 139 | |
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140 #define CYG_MSR_COMMON (MSR_FP | MSR_ME | MSR_RI) |
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141 |
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142 #if (CYGHWR_HAL_POWERPC_VECTOR_BASE == 0xfff00000) |
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143 # define IP_BIT MSR_IP |
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144 #else |
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145 # define IP_BIT 0 |
| 0 | 146 #endif |
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147 |
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148 #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU |
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149 # define IR_DR_BITS (MSR_IR | MSR_DR) |
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150 #else |
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151 # define IR_DR_BITS 0 |
| 0 | 152 #endif |
| 153 | |
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154 #define CYG_MSR (CYG_MSR_COMMON | IP_BIT | IR_DR_BITS) |
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155 |
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156 # Include variant macros after MSR definition. |
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157 #include <cyg/hal/arch.inc> |
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158 #include <cyg/hal/ppc_offsets.inc> |
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159 |
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160 |
| 2 | 161 #=========================================================================== |
| 0 | 162 # If the following option is enabled, we only save registers up to R12. |
| 163 # The PowerPC ABI defines registers 13..31 as callee saved and thus we do | |
| 164 # not need to save them when calling C functions. | |
| 165 | |
| 166 #ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT | |
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167 # define MAX_SAVE_REG 12 |
| 0 | 168 #else |
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169 # define MAX_SAVE_REG 31 |
| 0 | 170 #endif |
| 171 | |
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172 |
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173 #if defined(CYGHWR_HAL_POWERPC_NEED_VECTORS) |
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174 |
| 2 | 175 #=========================================================================== |
| 0 | 176 # Start by defining the exceptions vectors that must be placed at |
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177 # locations 0xFFF00000 or 0x00000000. The following code will normally |
| 0 | 178 # be located at 0xFFF00000 in the ROM. It may optionally be copied out |
| 179 # to 0x00000000 if we want to use the RAM vectors. For this reason this code | |
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180 # MUST BE POSITION INDEPENDENT. |
| 0 | 181 |
| 182 .section ".vectors","ax" | |
| 183 | |
| 2 | 184 #--------------------------------------------------------------------------- |
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185 # Macros for generating an exception vector service routine |
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186 |
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187 # Reset vector macro |
| 0 | 188 |
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189 .macro reset_vector name |
| 0 | 190 .p2align 8 |
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191 .globl __exception_\name |
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192 __exception_\name: |
| 473 | 193 #ifdef CYGSEM_HAL_POWERPC_RESET_USES_JUMP |
| 194 bl _start | |
| 195 #else | |
| 0 | 196 lwi r3,_start |
| 197 mtlr r3 | |
| 198 blr | |
| 473 | 199 #endif |
| 200 | |
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201 .endm |
| 0 | 202 |
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203 # Generic vector macro |
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204 |
| 0 | 205 .macro exception_vector name |
| 206 .p2align 8 | |
| 207 .globl __exception_\name | |
| 208 __exception_\name: | |
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209 mtspr SPRG1,r3 # stash some work registers away |
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210 mtspr SPRG2,r4 |
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211 mtspr SPRG3,r5 |
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212 mfcr r4 # stash CR |
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213 li r5,__exception_\name-rom_vectors # load low half of vector addr |
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214 srwi r5,r5,6 # shift right by 6 |
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215 lwi r3,hal_vsr_table # table base |
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216 lwzx r3,r3,r5 # address of vsr |
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217 mflr r5 # save link register |
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218 mtlr r3 # put vsr address into it |
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219 li r3,__exception_\name-rom_vectors # reload low half of vector addr |
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220 blr # go to common code |
| 0 | 221 .endm |
| 222 | |
| 2 | 223 #--------------------------------------------------------------------------- |
| 0 | 224 # Define the exception vectors. |
| 225 | |
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226 // Some platforms won't let us put the vector code just where we want |
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227 // This macro introduces some lattitude in vector placement |
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228 |
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229 #ifdef CYG_HAL_FUDGE_VECTOR_ALIGNMENT |
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230 hal_fudge_vector_alignment |
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231 #endif |
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232 |
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233 rom_vectors: |
| 0 | 234 # These are the architecture defined vectors that |
| 235 # are always present. | |
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236 #ifdef CYG_HAL_RESERVED_VECTOR_00000 |
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237 hal_reserved_vector_00000 |
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238 #else |
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239 exception_vector reserved_00000 |
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240 #endif |
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241 reset_vector reset |
| 0 | 242 exception_vector machine_check |
| 243 exception_vector data_storage | |
| 244 exception_vector instruction_storage | |
| 245 exception_vector external | |
| 246 exception_vector alignment | |
| 247 exception_vector program | |
| 248 exception_vector floatingpoint_unavailable | |
| 249 exception_vector decrementer | |
| 250 exception_vector reserved_00a00 | |
| 251 exception_vector reserved_00b00 | |
| 252 exception_vector system_call | |
| 253 exception_vector trace | |
| 254 exception_vector floatingpoint_assist | |
| 255 exception_vector reserved_00f00 | |
| 256 | |
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257 # Variants may define extra vectors. |
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258 hal_extra_vectors |
| 0 | 259 |
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260 rom_vectors_end: |
| 0 | 261 |
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262 #else // CYGHWR_HAL_POWERPC_NEED_VECTORS |
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263 |
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264 # When vectors are not included this is the primary entry point. |
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265 .globl __exception_reset |
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266 __exception_reset: |
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267 lwi r3,_start |
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268 mtlr r3 |
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269 blr |
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270 |
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271 #endif // CYGHWR_HAL_POWERPC_NEED_VECTORS |
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272 |
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273 |
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274 |
| 2 | 275 #=========================================================================== |
| 276 # Real startup code. We jump here from the various reset vectors to set up | |
| 277 # the world. | |
| 0 | 278 |
| 279 .text | |
| 280 .globl _start | |
| 2 | 281 _start: |
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282 # Initialize CPU to a post-reset state, ensuring the ground doesn''t |
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283 # shift under us while we try to set things up. |
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284 hal_cpu_init |
| 0 | 285 |
| 286 # Set up global offset table | |
| 287 lwi r2,_GLOBAL_OFFSET_TABLE_ | |
| 288 | |
| 289 # set up time base register to zero | |
| 290 xor r3,r3,r3 | |
| 2 | 291 mtspr TBL_W,r3 |
| 0 | 292 xor r4,r4,r4 |
| 2 | 293 mtspr TBU_W,r4 |
| 294 | |
| 295 # Call platform specific hardware initialization | |
| 296 # This may include memory controller initialization. It is not | |
| 297 # safe to access RAM until after this point. | |
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298 bl hal_hardware_init # this is platform dependent |
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299 .globl _hal_hardware_init_done |
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300 _hal_hardware_init_done: |
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301 |
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302 #if !defined(CYG_HAL_STARTUP_ROM) && defined(CYGSEM_HAL_POWERPC_COPY_VECTORS) |
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303 lwi r3,rom_vectors-4 |
| 1431 | 304 lwi r4,((CYGHWR_HAL_POWERPC_VECTOR_BASE)-4) |
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305 lwi r5,rom_vectors_end-4 |
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306 0: lwzu r0,4(r3) |
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307 stwu r0,4(r4) |
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308 cmplw r3,r5 |
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309 bne 0b |
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310 #endif |
| 0 | 311 |
| 312 # set up stack | |
| 313 lwi sp,__interrupt_stack | |
| 2 | 314 mtspr SPRG0,sp # save in sprg0 for later use |
| 0 | 315 |
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316 # Set up exception handlers and VSR table, taking care not to |
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317 # step on any ROM monitor''s toes. |
| 473 | 318 hal_mon_init |
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319 |
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320 #if defined(CYG_HAL_STARTUP_ROM) |
| 0 | 321 |
| 322 # Copy data from ROM to ram | |
| 323 lwi r3,__rom_data_start # r3 = rom start | |
| 324 lwi r4,__ram_data_start # r4 = ram start | |
| 325 lwi r5,__ram_data_end # r5 = ram end | |
| 326 | |
| 327 cmplw r4,r5 # skip if no data | |
| 328 beq 2f | |
| 329 | |
| 330 1: | |
| 331 lwz r0,0(r3) # get word from ROM | |
| 332 stw r0,0(r4) # store in RAM | |
| 333 addi r3,r3,4 # increment by 1 word | |
| 334 addi r4,r4,4 # increment by 1 word | |
| 335 cmplw r4,r5 # compare | |
| 336 blt 1b # loop if not yet done | |
| 337 2: | |
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338 #endif |
| 2 | 339 |
| 0 | 340 # clear BSS |
| 341 lwi r3,__bss_start # r3 = start | |
| 2 | 342 lwi r4,__bss_end # r4 = end |
| 0 | 343 li r0,0 # r0 = 0 |
| 344 cmplw r3,r4 # skip if no bss | |
| 345 beq 2f | |
| 346 | |
| 2 | 347 1: stw r0,0(r3) # store zero |
| 0 | 348 addi r3,r3,4 # increment by 1 word |
| 349 cmplw r3,r4 # compare | |
| 350 blt 1b # loop if not yet done | |
| 351 2: | |
| 352 | |
| 2 | 353 # clear SBSS |
| 354 lwi r3,__sbss_start # r3 = start | |
| 355 lwi r4,__sbss_end # r4 = end | |
| 356 cmplw r3,r4 # skip if no sbss | |
| 357 beq 2f | |
| 358 | |
| 359 1: stw r0,0(r3) # store zero | |
| 360 addi r3,r3,4 # increment by 1 word | |
| 361 cmplw r3,r4 # compare | |
| 362 blt 1b # loop if not yet done | |
| 363 2: | |
| 364 | |
| 365 # It is now safe to call C functions which may rely on initialized | |
| 366 # data. | |
| 367 | |
| 368 # Set up stack for calls to C code. | |
| 0 | 369 subi sp,sp,12 # make space on stack |
| 370 li r0,0 | |
| 371 stw r0,0(sp) # clear back chain | |
| 372 stw r0,8(sp) # zero return pc | |
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373 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 2 | 374 |
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375 # Variant HALs may need to do something special before we continue |
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376 bl hal_variant_init |
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377 |
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378 # Platform initialization |
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379 bl hal_platform_init |
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380 |
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381 # MMU and cache are controlled by the same option since caching |
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382 # on the PPC [typically] does not make sense without the MMU to mark |
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383 # regions which should not be cached. |
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384 #ifdef CYGHWR_HAL_POWERPC_ENABLE_MMU |
| 2 | 385 # Initialize MMU. |
| 386 bl hal_MMU_init | |
| 387 | |
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388 # Enable MMU (if desired) so we can safely enable caches. |
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389 lwi r3,CYG_MSR # interrupts enabled later |
| 2 | 390 sync |
| 391 mtmsr r3 | |
| 392 sync | |
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393 |
| 2 | 394 # Enable caches |
| 395 bl hal_enable_caches | |
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396 #endif // CYGHWR_HAL_POWERPC_ENABLE_MMU |
| 0 | 397 |
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398 # set up platform specific interrupt environment |
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399 bl hal_IRQ_init |
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400 |
| 2 | 401 # call c++ constructors |
| 402 bl cyg_hal_invoke_constructors | |
| 0 | 403 |
| 2 | 404 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
| 405 bl initialize_stub | |
| 0 | 406 #endif |
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407 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ |
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408 || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) |
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409 .extern hal_ctrlc_isr_init |
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410 bl hal_ctrlc_isr_init |
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411 #endif |
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412 |
| 0 | 413 bl cyg_start # call cyg_start |
| 414 9: | |
| 415 b 9b # if we return, loop | |
| 416 | |
| 2 | 417 #--------------------------------------------------------------------------- |
| 0 | 418 # This code handles the common part of all exception handlers. |
| 419 # It saves the machine state onto the stack and then calls | |
| 420 # a "C" routine to do the rest of the work. This work may result | |
| 421 # in thread switches, and changes to the saved state. When we return | |
| 422 # here the saved state is restored and execution is continued. | |
| 423 | |
| 424 .text | |
| 425 | |
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426 .globl cyg_hal_default_exception_vsr |
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427 cyg_hal_default_exception_vsr: |
| 0 | 428 |
| 429 # We come here with all register containing their | |
| 430 # pre-exception values except: | |
| 431 # R3 = ls 16 bits of vector address | |
| 432 # R4 = saved CR | |
| 433 # R5 = saved LR | |
| 434 # LR = VSR address | |
| 435 # SPRG1 = old R3 | |
| 436 # SPRG2 = old R4 | |
| 437 # SPRG3 = old R5 | |
| 438 # SRR0 = old PC | |
| 2 | 439 # SRR1 = old MSR and the exception cause (the POW state is lost!) |
| 0 | 440 |
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441 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT |
| 0 | 442 # leave space for registers and |
| 443 # a safety margin | |
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444 #ifdef CYGPKG_HAL_POWERPC_PPC40x |
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445 // The caches on this processor are always enabled when the MMU is on |
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446 // (and disabled when off). Thus we need to be careful about cache |
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447 // polution and staleness when changing the MMU state. |
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448 // At this point, the MMU is off due to the exception. We need to |
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449 // flush the part of the cache which may be touched before the MMU |
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450 // is reenabled so that memory will be consistent when that happens. |
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451 // Of course, this is complicated by the fact that there are no "free" |
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452 // registers at this point in the code. |
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453 dcbf 0,sp // Flushes first line |
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454 stw r3,0(sp) // This is now safe |
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455 li r3,CYGARC_PPCREG_VECTOR // Flush lines which will be changed |
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456 dcbf r3,sp |
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457 li r3,CYGARC_PPCREG_CR |
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458 dcbf r3,sp |
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459 li r3,CYGARC_PPCREG_LR |
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460 dcbf r3,sp |
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461 lwz r3,0(sp) // Restore register |
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462 #endif |
| 0 | 463 |
| 464 # First, save away some registers | |
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465 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector |
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466 stw r4,CYGARC_PPCREG_CR(sp) # stash CR |
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467 stw r5,CYGARC_PPCREG_LR(sp) # stash LR |
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468 |
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469 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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470 # Mark this fram as an Exception frame |
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471 lwi r3,0xDDDDDDE0 |
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472 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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473 lwi r3,0xDDDDDDE1 |
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474 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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475 #endif |
| 2 | 476 |
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477 # Enable MMU & interrupt/FPU environment (as configured) |
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478 lwi r3,CYG_MSR |
| 2 | 479 sync |
| 480 mtmsr r3 | |
| 481 sync | |
| 482 | |
| 483 mfspr r3,SPRG1 # save original R3 | |
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484 stw r3,CYGARC_PPCREG_REGS+3*4(sp) |
| 2 | 485 mfspr r4,SPRG2 # save original R4 |
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486 stw r4,CYGARC_PPCREG_REGS+4*4(sp) |
| 2 | 487 mfspr r5,SPRG3 # save original R5 |
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488 stw r5,CYGARC_PPCREG_REGS+5*4(sp) |
| 0 | 489 |
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490 stw r0,CYGARC_PPCREG_REGS+0*4(sp) # save R0 |
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491 stw r2,CYGARC_PPCREG_REGS+2*4(sp) # save R2 |
| 0 | 492 |
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493 mr r3,sp # recreate original SP |
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494 addi r3,r3,CYGARC_PPC_EXCEPTION_DECREMENT |
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495 stw r3,CYGARC_PPCREG_REGS+1*4(sp) # and save it in state |
| 0 | 496 |
| 2 | 497 # Save registers r6..r12/r31 |
| 0 | 498 .set _reg,6 |
| 499 .rept MAX_SAVE_REG+1-6 | |
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500 stw _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 501 .set _reg,_reg+1 |
| 502 .endr | |
| 503 | |
| 2 | 504 # Save registers used in vsr (r14+r15) |
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505 stw r14,(CYGARC_PPCREG_REGS+14*4)(sp) |
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506 stw r15,(CYGARC_PPCREG_REGS+15*4)(sp) |
| 2 | 507 |
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508 # get remaining family CPU registers |
| 0 | 509 mfxer r3 |
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510 mfctr r4 |
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511 mfsrr0 r5 |
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512 mfsrr1 r6 |
| 0 | 513 # and store them |
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514 stw r3,CYGARC_PPCREG_XER(sp) |
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515 stw r4,CYGARC_PPCREG_CTR(sp) |
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516 stw r5,CYGARC_PPCREG_PC(sp) |
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517 stw r6,CYGARC_PPCREG_MSR(sp) |
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518 |
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519 # Save variant registers |
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520 hal_variant_save sp |
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521 |
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522 # Save FPU registers |
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523 hal_fpu_save sp |
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524 |
| 0 | 525 # The entire CPU state is now stashed on the stack, |
| 526 # call into C to do something with it. | |
| 527 | |
| 528 mr r3,sp # R3 = register dump | |
| 529 | |
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530 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 531 |
| 532 li r0,0 # R0 = 0 | |
| 533 stw r0,0(sp) # backchain = 0 | |
| 534 stw r0,8(sp) # return pc = 0 | |
| 535 | |
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536 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 537 # where C code can save LR |
| 538 | |
| 539 lwi r5,restore_state # get return link | |
| 540 mtlr r5 # to link register | |
| 541 | |
| 2 | 542 .extern cyg_hal_exception_handler |
| 543 b cyg_hal_exception_handler # call C code, r3 = registers | |
| 0 | 544 |
| 545 # When the call returns it will go to restore_state below. | |
| 546 | |
| 547 | |
| 2 | 548 ##-------------------------------------------------------------------------- |
| 549 ## The following macros are defined depending on whether the Interrupt | |
| 550 ## system is using isr tables or chaining, and depending on the interrupt | |
| 551 ## controller in the system. | |
| 552 | |
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553 #ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED |
| 2 | 554 |
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555 ## This is the simple version. No interrupt controller, CYGARC_PPCREG_VECTOR |
| 2 | 556 ## is updated with the decoded interrupt vector. Isr tables/chaining |
| 557 ## use same interrupt decoder. | |
| 558 ## Bit 21 biffers between decrementer (0) and external (1). | |
| 559 | |
| 560 # decode the interrupt | |
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561 .macro hal_intc_decode dreg,state |
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562 lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number, |
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563 rlwinm \dreg,\dreg,22,31,31 # isolate bit 21 and update |
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564 stw \dreg,CYGARC_PPCREG_VECTOR(\state) # vector in state frame. |
|
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565 slwi \dreg,\dreg,2 # convert to word offset. |
| 2 | 566 .endm |
| 567 | |
|
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568 #endif // CYGPKG_HAL_POWERPC_INTC_DEFINED |
| 2 | 569 |
| 570 #--------------------------------------------------------------------------- | |
| 0 | 571 # Common interrupt handling code. |
| 572 | |
|
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573 .globl cyg_hal_default_interrupt_vsr |
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574 cyg_hal_default_interrupt_vsr: |
| 0 | 575 |
| 576 # We come here with all register containing their | |
| 577 # pre-exception values except: | |
| 578 # R3 = ls 16 bits of vector address | |
| 579 # R4 = saved CR | |
| 580 # R5 = saved LR | |
| 581 # LR = VSR address | |
| 582 # SPRG1 = old R3 | |
| 583 # SPRG2 = old R4 | |
| 584 # SPRG3 = old R5 | |
| 585 # SRR0 = old PC | |
| 586 # SRR1 = old MSR | |
| 587 | |
| 588 | |
|
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589 subi sp,sp,CYGARC_PPC_EXCEPTION_DECREMENT |
| 0 | 590 # leave space for registers and |
| 591 # a safety margin | |
|
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592 #ifdef CYGPKG_HAL_POWERPC_PPC40x |
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593 // The caches on this processor are always enabled when the MMU is on |
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594 // (and disabled when off). Thus we need to be careful about cache |
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595 // polution and staleness when changing the MMU state. |
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596 // At this point, the MMU is off due to the exception. We need to |
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597 // flush the part of the cache which may be touched before the MMU |
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598 // is reenabled so that memory will be consistent when that happens. |
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599 // Of course, this is complicated by the fact that there are no "free" |
|
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600 // registers at this point in the code. |
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601 dcbf 0,sp // Flushes first line |
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602 stw r3,0(sp) // This is now safe |
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603 li r3,CYGARC_PPCREG_VECTOR // Flush lines which will be changed |
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604 dcbf r3,sp |
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605 li r3,CYGARC_PPCREG_CR |
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606 dcbf r3,sp |
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607 li r3,CYGARC_PPCREG_LR |
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608 dcbf r3,sp |
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609 lwz r3,0(sp) // Restore register |
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610 #endif |
|
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611 |
|
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612 stw r3,CYGARC_PPCREG_VECTOR(sp) # stash vector |
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613 stw r4,CYGARC_PPCREG_CR(sp) # stash CR |
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614 stw r5,CYGARC_PPCREG_LR(sp) # stash LR |
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615 |
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616 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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617 # Mark this fram as an 1nterrupt frame |
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618 lwi r3,0xDDDDDD10 |
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619 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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620 lwi r3,0xDDDDDD11 |
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621 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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622 #endif |
| 0 | 623 |
|
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624 # Enable MMU & interrupt/FPU environment as configured |
|
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625 lwi r3,CYG_MSR |
| 2 | 626 sync |
| 627 mtmsr r3 | |
| 628 sync | |
| 629 | |
| 630 mfspr r3,SPRG1 # save original R3 | |
|
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631 stw r3,CYGARC_PPCREG_REGS+3*4(sp) |
| 2 | 632 mfspr r4,SPRG2 # save original R4 |
|
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633 stw r4,CYGARC_PPCREG_REGS+4*4(sp) |
| 2 | 634 mfspr r5,SPRG3 # save original R5 |
|
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635 stw r5,CYGARC_PPCREG_REGS+5*4(sp) |
| 0 | 636 |
|
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637 stw r0,CYGARC_PPCREG_REGS+0*4(sp) # save R0 |
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638 stw r2,CYGARC_PPCREG_REGS+2*4(sp) # save R2 |
| 0 | 639 |
|
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640 mr r3,sp # recreate original SP |
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641 addi r3,r3,CYGARC_PPC_EXCEPTION_DECREMENT |
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642 stw r3,CYGARC_PPCREG_REGS+1*4(sp) # and save it in state |
| 0 | 643 |
| 2 | 644 # Save registers r6..r12/r31 |
| 0 | 645 .set _reg,6 |
| 646 .rept MAX_SAVE_REG+1-6 | |
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647 stw _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 648 .set _reg,_reg+1 |
| 649 .endr | |
| 650 | |
| 2 | 651 # Save registers used in vsr (r14+r15) |
|
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652 stw r14,CYGARC_PPCREG_REGS+14*4(sp) |
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653 stw r15,CYGARC_PPCREG_REGS+15*4(sp) |
| 2 | 654 |
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655 # get remaining family CPU registers |
| 0 | 656 mfxer r3 |
|
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657 mfctr r4 |
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658 mfsrr0 r5 |
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659 mfsrr1 r6 |
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660 |
| 0 | 661 # and store them |
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662 stw r3,CYGARC_PPCREG_XER(sp) |
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663 stw r4,CYGARC_PPCREG_CTR(sp) |
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664 stw r5,CYGARC_PPCREG_PC(sp) |
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665 stw r6,CYGARC_PPCREG_MSR(sp) |
| 0 | 666 |
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667 # Save variant registers |
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668 hal_variant_save sp |
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669 |
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670 # Save FPU registers |
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671 hal_fpu_save sp |
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672 |
| 0 | 673 # The entire CPU state is now stashed on the stack, |
| 674 # increment the scheduler lock and call the ISR | |
| 675 # for this vector. | |
| 676 | |
| 677 #ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT | |
| 2 | 678 .extern cyg_scheduler_sched_lock |
| 679 lwi r3,cyg_scheduler_sched_lock | |
| 0 | 680 lwz r4,0(r3) |
| 681 addi r4,r4,1 | |
| 682 stw r4,0(r3) | |
| 683 #endif | |
| 684 | |
| 2 | 685 mr r14,sp # r14 = register dump |
| 0 | 686 |
| 687 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 688 lwi r3,__interrupt_stack # stack top | |
| 689 lwi r4,__interrupt_stack_base # stack base | |
| 690 sub. r5,sp,r4 # sp - base | |
| 691 blt 1f # if < 0 - not on istack | |
| 692 sub. r5,r3,sp # top - sp | |
| 693 bgt 2f # if > 0 - already on istack | |
| 694 | |
| 695 1: mr sp,r3 # switch to istack | |
| 696 | |
| 2 | 697 2: stwu r14,-4(sp) # save old SP on stack |
| 0 | 698 |
| 699 #endif | |
| 700 | |
|
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701 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 702 |
| 703 li r0,0 # R0 = 0 | |
| 704 stw r0,0(sp) # backchain = 0 | |
| 705 stw r0,8(sp) # return pc = 0 | |
| 706 | |
|
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707 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 708 # where C code can save LR |
| 709 | |
| 710 #if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) | |
| 711 | |
| 712 lwi r3,0x0301 # r3 = type = INTR,RAISE | |
|
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713 lwz r4,CYGARC_PPCREG_VECTOR(r14) # arg1 = vector address |
| 0 | 714 srwi r4,r4,8 # arg1 = vector number |
| 715 xor r5,r5,r5 # arg2 = 0 | |
| 716 bl cyg_instrument # call instrument function | |
| 717 | |
| 718 #endif | |
| 719 | |
|
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720 hal_intc_decode r15,r14 # get table index |
| 2 | 721 |
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722 #if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \ |
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723 || defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT) |
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724 # If we are supporting Ctrl-C interrupts from GDB, we must squirrel |
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725 # away a pointer to the save interrupt state here so that we can |
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726 # plant a breakpoint at some later time. |
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727 |
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728 .extern hal_saved_interrupt_state |
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729 lwi r3,hal_saved_interrupt_state |
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730 stw r14,0(r3) |
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731 |
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732 #endif |
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733 |
| 2 | 734 #ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING |
| 0 | 735 |
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736 #ifdef CYGPKG_HAL_POWERPC_MPC8xx |
| 2 | 737 # The CPM controller allows nested interrupts. However, |
| 738 # it sits on the back of the SIU controller which has no | |
| 739 # HW support for this. In effect, SW masking of lower | |
| 740 # priority IRQs in the SIU would be required for this to work. | |
| 741 #endif | |
| 742 | |
| 743 #endif | |
| 744 | |
|
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745 lwz r3,CYGARC_PPCREG_VECTOR(r14) # retrieve decoded vector # |
| 0 | 746 |
| 747 lwi r6,hal_interrupt_handlers # get interrupt handler table | |
| 748 lwzx r6,r6,r15 # load routine pointer | |
| 749 | |
| 750 lwi r4,hal_interrupt_data # get interrupt data table | |
| 751 lwzx r4,r4,r15 # load data pointer | |
| 752 # R4 = data argument | |
| 423 | 753 mr r5,r14 # R5 = saved registers |
| 0 | 754 |
| 755 mtctr r6 # put isr address in ctr | |
| 756 | |
| 757 bctrl # branch to ctr reg and link | |
| 758 | |
| 759 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK | |
| 760 | |
| 761 # If we are returning from the last nested interrupt, move back | |
| 762 # to the thread stack. interrupt_end() must be called on the | |
| 763 # thread stack since it potentially causes a context switch. | |
| 764 # Since we have arranged for the top of stack location to | |
| 765 # contain the sp we need to go back to here, just pop it off | |
| 766 # and put it in SP. | |
| 767 | |
| 768 | |
|
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769 lwz sp,CYGARC_PPC_STACK_FRAME_SIZE*2(sp) # sp = *sp |
| 0 | 770 |
|
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771 subi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE # make a null frame |
| 0 | 772 |
| 773 li r0,0 # R0 = 0 | |
| 774 stw r0,0(sp) # backchain = 0 | |
| 775 stw r0,8(sp) # return pc = 0 | |
| 776 | |
|
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777 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) # create new stack frame |
| 0 | 778 # where C code can save LR |
| 779 #endif | |
| 780 | |
|
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781 # On return r3 bit 1 will indicate whether a DSR is |
| 0 | 782 # to be posted. Pass this together with a pointer to |
| 783 # the interrupt object we have just used to the | |
| 784 # interrupt tidy up routine. | |
| 785 | |
| 2 | 786 # Note that r14 and r15 are defined to be preserved across |
| 0 | 787 # calls by the calling convention, so they still contain |
| 788 # the register dump and the vector number respectively. | |
| 2 | 789 |
| 0 | 790 lwi r4,hal_interrupt_objects # get interrupt object table |
| 791 lwzx r4,r4,r15 # load object pointer | |
|
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792 mr r5,r14 # arg3 = saved register dump |
| 0 | 793 |
| 794 .extern interrupt_end | |
| 795 bl interrupt_end # call into C to finish off | |
| 796 | |
| 797 restore_state: | |
| 798 # All done, restore CPU state and continue | |
| 799 | |
|
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800 # retrieve CPU state pointer |
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801 addi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE*2 |
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802 |
|
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803 # Restore FPU registers |
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804 hal_fpu_load sp |
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805 |
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806 # Restore variant registers |
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807 hal_variant_load sp |
| 0 | 808 |
| 809 # get sprs we want to restore | |
|
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810 # stuff some of them into the CPU |
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811 lwz r3,CYGARC_PPCREG_XER(sp) |
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812 lwz r4,CYGARC_PPCREG_LR(sp) |
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813 lwz r5,CYGARC_PPCREG_CTR(sp) |
|
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814 mtxer r3 |
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815 mtlr r4 |
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816 mtctr r5 |
| 0 | 817 |
| 2 | 818 # Restore registers used in vsr (r14+r15) |
|
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819 lwz r14,CYGARC_PPCREG_REGS+14*4(r1) |
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820 lwz r15,CYGARC_PPCREG_REGS+15*4(r1) |
| 2 | 821 |
| 822 # restore registers r6..r12/r31 | |
| 0 | 823 .set _reg,6 |
| 824 .rept MAX_SAVE_REG+1-6 | |
|
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825 lwz _reg,(CYGARC_PPCREG_REGS+_reg*4)(sp) |
| 0 | 826 .set _reg,_reg+1 |
| 827 .endr | |
| 828 | |
|
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829 hal_cpu_int_disable |
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830 |
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831 # restore R0 and R2 |
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832 lwz r0,CYGARC_PPCREG_REGS+0*4(sp) |
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833 lwz r2,CYGARC_PPCREG_REGS+2*4(sp) |
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834 |
| 0 | 835 # Here all the registers are loaded except |
|
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836 # sp = HAL_SavedRegisters |
| 0 | 837 # r3 = ccr |
| 838 # r4 = srr0 = pc | |
| 839 # r5 = srr1 = msr | |
|
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840 # |
| 0 | 841 # We have to disable interrupts while srr0 and |
| 842 # srr1 are loaded, since another interrupt will | |
| 843 # destroy them. | |
| 844 | |
|
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845 lwz r3,CYGARC_PPCREG_CR(sp) |
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846 lwz r4,CYGARC_PPCREG_PC(sp) |
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847 lwz r5,CYGARC_PPCREG_MSR(sp) |
| 0 | 848 mtcr r3 # set ccr |
| 849 mtsrr0 r4 # load old pc | |
| 850 mtsrr1 r5 # load old msr | |
| 851 | |
|
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852 #ifdef CYGDBG_HAL_POWERPC_FRAME_WALLS |
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853 # Mark this frame as (almost) dead. |
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854 lwi r3,0xDDDDDDD0 |
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855 stw r3,CYGARC_PPCREG_WALL_HEAD(sp) |
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856 lwi r3,0xDDDDDDD1 |
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857 stw r3,CYGARC_PPCREG_WALL_TAIL(sp) |
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858 #endif |
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859 |
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860 lwz r3,CYGARC_PPCREG_REGS+3*4(sp) # load r3 value |
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861 lwz r4,CYGARC_PPCREG_REGS+4*4(sp) # load r4 value |
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862 lwz r5,CYGARC_PPCREG_REGS+5*4(sp) # load r5 value |
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863 lwz sp,CYGARC_PPCREG_REGS+1*4(sp) # restore sp |
| 0 | 864 |
| 865 sync # settle things down | |
| 866 isync | |
| 867 rfi # and return | |
| 868 | |
|
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869 |
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870 |
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871 ##----------------------------------------------------------------------------- |
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872 ## Execute pending DSRs on the interrupt stack with interrupts enabled. |
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873 ## Note: this can only be called from code running on a thread stack |
|
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874 |
|
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875 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
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876 .extern cyg_interrupt_call_pending_DSRs |
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877 |
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878 FUNC_START(hal_interrupt_stack_call_pending_DSRs) |
|
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879 # Change to interrupt stack, save state and set up stack for |
|
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880 # calls to C code. |
|
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881 mr r3,sp |
|
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882 lwi r4,__interrupt_stack |
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883 subi r4,r4,24 # make space on stack |
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884 mr sp,r4 |
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885 stw r3,12(sp) # save old sp |
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886 mfmsr r3 |
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887 stw r3,16(sp) # save old MSR |
|
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888 mflr r3 |
|
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889 stw r3,20(sp) # save old LR |
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890 |
|
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891 li r0,0 |
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892 stw r0,0(sp) # clear back chain |
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893 stw r0,8(sp) # zero return pc |
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894 |
|
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895 hal_cpu_int_enable |
|
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896 |
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897 # Call into kernel which will execute DSRs |
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898 stwu sp,-CYGARC_PPC_STACK_FRAME_SIZE(sp) |
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899 bl cyg_interrupt_call_pending_DSRs |
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900 addi sp,sp,CYGARC_PPC_STACK_FRAME_SIZE |
|
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901 |
|
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902 lwz r3,20(sp) # restore LR |
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903 mtlr r3 |
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|
904 lwz r5,12(sp) # get SP from saved state |
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905 lwz r3,16(sp) # restore interrupt setting |
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906 hal_cpu_int_merge r3 |
|
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907 |
|
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908 mr sp,r5 # restore stack pointer |
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909 blr # and return to caller |
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910 #endif |
|
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911 |
| 2 | 912 #--------------------------------------------------------------------------- |
| 0 | 913 ## Temporary interrupt stack |
| 914 | |
| 915 .section ".bss" | |
| 916 | |
| 917 .balign 16 | |
|
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918 .global cyg_interrupt_stack_base |
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|
919 cyg_interrupt_stack_base: |
| 0 | 920 __interrupt_stack_base: |
| 921 .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE | |
| 922 .byte 0 | |
| 923 .endr | |
| 924 .balign 16 | |
|
8
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
925 .global cyg_interrupt_stack |
|
ece80412419a
Merge from eCos master repository on 1999-05-21-22:05:54-BST
jlarmour
parents:
2
diff
changeset
|
926 cyg_interrupt_stack: |
| 0 | 927 __interrupt_stack: |
| 928 | |
| 929 .long 0,0,0,0,0,0,0,0 | |
| 930 | |
| 2 | 931 #--------------------------------------------------------------------------- |
| 0 | 932 # end of vectors.S |